FPGA Central

I am trying to use Xilinx chipscope, but it is not working properly
(probably mishandling by the user...). Perhaps somebody can give me
some light...

I used core inserter, and I have a ICON and a ILA core.
I want to monitor a SPI bus in a 2VP2 device, that has 12 RAM blocks
available.
I defined a 1 trigger port with width 1, set with the sclk (that
should be around 10MHz).
And I have a 40 data width bus where I try to see many data signals.

I can go to the point where I generate the programming file (bit file).
Startup clock is set to JTAGclk, keep hierarchy is set to YES. I also
generate (just in case) the mcs file and load my 18V04 EEPROM. I
recicle power and then I click in the Analyze Design Using Chipscope.
After opening the JTAG Chain (XILINX Parallel IV cable), it says that
it found 1 core unit in the JTAG device Chain. But if I press the
"trigger now" button, it does not give me the status of the lines. It
enters a mode where it says"siting for core to be armed." and stays
there forever. Am I setting the trigger in a wrong way?

We are talking about versions 7.1 os ISE and chipscope pro.

I would appreciate any input!

Roberto schrieb:
> I am trying to use Xilinx chipscope, but it is not working properly
> (probably mishandling by the user...). Perhaps somebody can give me
> some light...
>
> I used core inserter, and I have a ICON and a ILA core.
> I want to monitor a SPI bus in a 2VP2 device, that has 12 RAM blocks
> available.
> I defined a 1 trigger port with width 1, set with the sclk (that
> should be around 10MHz).
> And I have a 40 data width bus where I try to see many data signals.
>
> I can go to the point where I generate the programming file (bit file).
> Startup clock is set to JTAGclk, keep hierarchy is set to YES. I also
> generate (just in case) the mcs file and load my 18V04 EEPROM. I
> recicle power and then I click in the Analyze Design Using Chipscope.
> After opening the JTAG Chain (XILINX Parallel IV cable), it says that
> it found 1 core unit in the JTAG device Chain. But if I press the
> "trigger now" button, it does not give me the status of the lines. It
> enters a mode where it says"siting for core to be armed." and stays
> there forever. Am I setting the trigger in a wrong way?
>
> We are talking about versions 7.1 os ISE and chipscope pro.
>
> I would appreciate any input!
>
Hi,

Did you Configure the Trigger?
Think of ChipScope as a Scope. If you do it similar, it will work

Cheers
Marc

Roberto wrote:
> I am trying to use Xilinx chipscope, but it is not working properly
> (probably mishandling by the user...). Perhaps somebody can give me
> some light...
>
> I used core inserter, and I have a ICON and a ILA core.
> I want to monitor a SPI bus in a 2VP2 device, that has 12 RAM blocks
> available.
> I defined a 1 trigger port with width 1, set with the sclk (that
> should be around 10MHz).
> And I have a 40 data width bus where I try to see many data signals.
>
> I can go to the point where I generate the programming file (bit file).
> Startup clock is set to JTAGclk, keep hierarchy is set to YES. I also
> generate (just in case) the mcs file and load my 18V04 EEPROM. I
> recicle power and then I click in the Analyze Design Using Chipscope.
> After opening the JTAG Chain (XILINX Parallel IV cable), it says that
> it found 1 core unit in the JTAG device Chain. But if I press the
> "trigger now" button, it does not give me the status of the lines. It
> enters a mode where it says"siting for core to be armed." and stays
> there forever. Am I setting the trigger in a wrong way?
>
> We are talking about versions 7.1 os ISE and chipscope pro.
>
> I would appreciate any input!
>
just press the immediate sample/trigger button if you do not want to
trigger for an event but just see the 'current' signal values ...

OR setup the right triggers like Markus Meng said

Yeah, the core is not getting a clock signal. You stated that you
connected SCLK to the trigger port of ChipScope. Is that really what
you meant? If so, you never stated what the CLK port of chipScope is
connected to, if anything.

Roberto wrote:

> "trigger now" button, it does not give me the status of the lines. It
> enters a mode where it says"siting for core to be armed." and stays
> there forever. Am I setting the trigger in a wrong way?
>
Usually if ChipScope doesn't respond to "trigger now" that means that
the ILA core is getting no clock input.
-Kevin