FPGA Central

Hey guys,

I've just put an image processing design onto my Nexys 2 (S3E500) and
have started using ChipScope for the first time to suss it all out. To
my suprise, my FVAL and LVAL signals seem to be all over the shop.

In the picture, ports 5 and 6 are just random pixels, as they are
behaving as expected: toggling around for 320 clocks, asserted low for
80. This matches the supposed LVAL timing on the camera data sheet.
Unfortunately, port 1 is LVAL, and as you can see it maintains some
sense of order, but is certainly not clean. It is up/toggling for the
320 clocks, then generally low for the 80.

FVAL, at the top, should be high for all of this, but like LVAL
toggles around. Initially I expected that the lines are absorbing some
noise, since I have it hooked up with a custom crimp header adapter
(since the Nexys doesn't have an MDR26 of course). The confusing part
then, is that LVAL toggles religiously when FVAL is de-asserted.

The camera is a JAI Pulnix TM 6740 CL

http://farm4.static.flickr.com/3461/...6270e6.jpg?v=0
http://farm4.static.flickr.com/3297/...67b993.jpg?v=0

Grabs aren't great but hopefully they shed some light.

Any ideas on what could be the problems?

1 more things I should have added:

I have used XAPP485 to do the deserializing of the stream.

Hi,
just some questions:
Is the analog video output working correctly?
Is the camera configured properly?
Do you have noise on the external sync input?

In the first picture FVAL is going low four times with three different
durations. Is that a sampling problem, or is there a meaning behind it?

The toggling of the LVAL signal during FVAL-low phases looks strange,
but may be part of the cameras design. You should ask pulnix for
detailed specs of their FVAL/LVAL/DVAL structure.

The second picture looks good as far as FVAL stays high, while LVAL is
going low. Of course there's lot's of noise in the signal.

Is your power supply working correctly and stable enough for this camera?
Is your camera Link cable properly terminated?
Are there other noise sources? e.g. Ground loops, bad (noisy) FPGA power
supply, insufficent power capacitors, noisy working area?

Regards
Eilert

[email protected] schrieb:
> Hey guys,
>
> I've just put an image processing design onto my Nexys 2 (S3E500) and
> have started using ChipScope for the first time to suss it all out. To
> my suprise, my FVAL and LVAL signals seem to be all over the shop.
>
> In the picture, ports 5 and 6 are just random pixels, as they are
> behaving as expected: toggling around for 320 clocks, asserted low for
> 80. This matches the supposed LVAL timing on the camera data sheet.
> Unfortunately, port 1 is LVAL, and as you can see it maintains some
> sense of order, but is certainly not clean. It is up/toggling for the
> 320 clocks, then generally low for the 80.
>
> FVAL, at the top, should be high for all of this, but like LVAL
> toggles around. Initially I expected that the lines are absorbing some
> noise, since I have it hooked up with a custom crimp header adapter
> (since the Nexys doesn't have an MDR26 of course). The confusing part
> then, is that LVAL toggles religiously when FVAL is de-asserted.
>
> The camera is a JAI Pulnix TM 6740 CL
>
> http://farm4.static.flickr.com/3461/...6270e6.jpg?v=0
> http://farm4.static.flickr.com/3297/...67b993.jpg?v=0
>
> Grabs aren't great but hopefully they shed some light.
>
> Any ideas on what could be the problems?

On Feb 2, 12:41*am, reganirel...@gmail.com wrote:
> 1 more things I should have added:
>
> I have used XAPP485 to do the deserializing of the stream.

Camera Link puts FVAL and LVAL in the same LVDS pair
for the channel link interface. So it is possible that
only that one pair has some signal integrity problem,
possibly too much skew to the clock pair? If that is
the case and the other pairs work OK, you could get
good pixel data while the FVAL and LVAL signals bounce
around.

Regards,
Gabor

On Feb 2, 11:50 pm, Gabor <ga...@alacron.com> wrote:
> On Feb 2, 12:41 am, reganirel...@gmail.com wrote:
>
> > 1 more things I should have added:
>
> > I have used XAPP485 to do the deserializing of the stream.
>
> Camera Link puts FVAL and LVAL in the same LVDS pair
> for the channel link interface. So it is possible that
> only that one pair has some signal integrity problem,
> possibly too much skew to the clock pair? If that is
> the case and the other pairs work OK, you could get
> good pixel data while the FVAL and LVAL signals bounce
> around.
>
> Regards,
> Gabor

Yes, that is what I'm hoping is the problem, solely the RX2 pair where
DVAL/FVAL/LVAL are consecutive. The pixel data looks very well
behaved, bouncing around on clock edges for 320 clocks (2 taps, 320
each, 640pix wide image), then dead low for 80pix. I have few doubts
now that the problem lies in the way I have connected the camera to
the FPGA dev board: from an MDR26 connector fly-wired to some 2.54mm
crimps. I know eventually I will need a proper board, but I hoped to
get a bit of prototyping done without much outlay...

Going to talk to some others about how better to shield the LVDS
pairs, particularly RX2.

Regan