FPGA Central

Hello All,

I have 3 burning, if fundamental questions about FPGA architecture.

1) When the term routing is used, does it include the switch block
multiplexers and the interconnections (Long wires, short wires etc.)?

2) When packing it done well, can I say that LUTs are packed close to
each other so the amount of routing resources used is less?

3) For Altera FPGAs (eg. Stratix versions), how are the LUTs
implemented? For Xilinx, its generally distributed RAM. For Altera
which only uses coarse-grain memory, this can't be the case so what is
the alternative?

tEd

Ted wrote:
>
> Hello All,
>
> I have 3 burning, if fundamental questions about FPGA architecture.
>
> 1) When the term routing is used, does it include the switch block
> multiplexers and the interconnections (Long wires, short wires etc.)?

I normally am referring to both the interconnect lines as well as the
switches and multiplexors when I use the term routing.


> 2) When packing it done well, can I say that LUTs are packed close to
> each other so the amount of routing resources used is less?

You would thinks so. But I am sure there are mitigating factors. For
example, if you have large data busses that need to run on long routes
anyway, it is not so important to minimize the length of these nets
while other logic such as FSM (finite state machines) will be well
served by short routes. So it is a design dependant issue.


> 3) For Altera FPGAs (eg. Stratix versions), how are the LUTs
> implemented? For Xilinx, its generally distributed RAM. For Altera
> which only uses coarse-grain memory, this can't be the case so what is
> the alternative?

I believe the LUTs are still RAM based in Altera FPGAs. You just can't
use the LUT as a small ram block. I expect Xilinx has a patent on
that. But patents expire eventually. So it may not be too long before
Altera also has distributed ram... likely about the time when no one
cares anymore

--

Rick "rickman" Collins

[email protected]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

Ted wrote:

> I have 3 burning, if fundamental questions about FPGA architecture.

> 1) When the term routing is used, does it include the switch block
> multiplexers and the interconnections (Long wires, short wires etc.)?

Different architectures are different, but I would include everything
except LUT data bits, carry chain configuration, and IOB configuration.
Inputs to LUT's, FF's, and IOB's usually come from mux's, which are,
to me, routing.

> 2) When packing it done well, can I say that LUTs are packed close to
> each other so the amount of routing resources used is less?

Maybe. If you use the carry chain that fixes the relative position
of many CLBs. That can restrict the routing such that close
packing increases the routing problems.

Also, as the device gets full and routing resources get low, the
router can make some very long routes, including through LUTs.

If the device is not very full, there isn't much constraint on
the routing and some routers will spread the logic out.

> 3) For Altera FPGAs (eg. Stratix versions), how are the LUTs
> implemented? For Xilinx, its generally distributed RAM. For Altera
> which only uses coarse-grain memory, this can't be the case so what is
> the alternative?

It is, I believe, a course array of RAM, DSP, and LAB blocks,
where the LAB blocks internally contain LUT's and routing
resources, and then routing between the different kinds of blocks.

http://www.altera.com/literature/hb/stx/ch_2_vol_1.pdf

-- glen

Hi Glen, Rick,

I can see what you guys are saying. Thanks for the clarification about
semantics. I think that the bit about packing is very interesting. I
agree that the dependence of routing resources on packing is dependant
on the amount of routing and logic resources left over but I guess
that the more efficiently the logic is packed, the slower we will hit
the threshold that would place severe constraints on routing and
mapping. Correct me if I am wrong.

Also, the part on the use of carry chains could produce routing
problems make sense. However, if the carry chain is not used, more
routing resources would need to be used to link the carries from 1
cell to another. For arithmetic rich operations, this could be a
problem.

It seems to me that relationship between routing resources and packing
efficiency is pretty strong across most aplications. Again, feel free
to refute me. Thanks.

tEd

glen herrmannsfeldt <[email protected]> wrote in message news:<cicins$usv$[email protected]>...
> Ted wrote:
>
> > I have 3 burning, if fundamental questions about FPGA architecture.
>
> > 1) When the term routing is used, does it include the switch block
> > multiplexers and the interconnections (Long wires, short wires etc.)?
>
> Different architectures are different, but I would include everything
> except LUT data bits, carry chain configuration, and IOB configuration.
> Inputs to LUT's, FF's, and IOB's usually come from mux's, which are,
> to me, routing.
>
> > 2) When packing it done well, can I say that LUTs are packed close to
> > each other so the amount of routing resources used is less?
>
> Maybe. If you use the carry chain that fixes the relative position
> of many CLBs. That can restrict the routing such that close
> packing increases the routing problems.
>
> Also, as the device gets full and routing resources get low, the
> router can make some very long routes, including through LUTs.
>

> If the device is not very full, there isn't much constraint on
> the routing and some routers will spread the logic out.
>
> > 3) For Altera FPGAs (eg. Stratix versions), how are the LUTs
> > implemented? For Xilinx, its generally distributed RAM. For Altera
> > which only uses coarse-grain memory, this can't be the case so what is
> > the alternative?
>
> It is, I believe, a course array of RAM, DSP, and LAB blocks,
> where the LAB blocks internally contain LUT's and routing
> resources, and then routing between the different kinds of blocks.
>
> http://www.altera.com/literature/hb/stx/ch_2_vol_1.pdf
>
> -- glen