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Old 12-09-2003, 12:21 PM
Przemyslaw Wegrzyn
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Default BUFT resources in Spartan II

Hi !

In the spartan datasheet I can read that:

"Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row"

What does partitionable mean in this case ? Does this mean the
horizontal lines can be divided ? If so, where (how many) the division
points are there ?


Is FPGA Editor removed from ISE6.1i ? I've recently used 6.1i at my
university, and couldn't find it
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Old 12-09-2003, 11:16 PM
John_H
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Default Re: BUFT resources in Spartan II

Every 4 CLBs, the horizontal tristate line has a pip, delivering the
partitioning you read about. Only one of the four horizontal lines has a
pip at each CLB column giving a staggered partitioning. Those lines can
also interface with the IOBs on the left and right side of the device. They
aren't "real" tristates in that if you drive a 1 and a 0 into the same line,
the chip doesn't complain with smoke and heat - it gives you the low logic
level.

FPGA Editor is in the 6.1 tools, but I understand it's not a WebPack item.
(I could be mistaken on this)


"Przemyslaw Wegrzyn" <[email protected]> wrote in message
news:[email protected] om...
> Hi !
>
> In the spartan datasheet I can read that:
>
> "Horizontal routing resources are provided for on-chip
> 3-state busses. Four partitionable bus lines are
> provided per CLB row"
>
> What does partitionable mean in this case ? Does this mean the
> horizontal lines can be divided ? If so, where (how many) the division
> points are there ?
>
>
> Is FPGA Editor removed from ISE6.1i ? I've recently used 6.1i at my
> university, and couldn't find it



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  #3 (permalink)  
Old 12-10-2003, 10:17 AM
Przemyslaw Wegrzyn
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Default Re: BUFT resources in Spartan II

"John_H" <[email protected]> wrote in message news:<JQrBb.13$[email protected]>...
> Every 4 CLBs, the horizontal tristate line has a pip, delivering the
> partitioning you read about. Only one of the four horizontal lines has a
> pip at each CLB column giving a staggered partitioning. Those lines can
> also interface with the IOBs on the left and right side of the device. They


Thanks, this is exactly what I wnated to know.

> aren't "real" tristates in that if you drive a 1 and a 0 into the same line,
> the chip doesn't complain with smoke and heat - it gives you the low logic
> level.


Yes, this info I've seen somewhere in the group archives.

> FPGA Editor is in the 6.1 tools, but I understand it's not a WebPack item.
> (I could be mistaken on this)


Unfortunately it was the case - it was WebPack installed on this
machine. I'll get access to full installation at university soon

Thanks !
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