FPGA Central

Hi

Probably a quite popular question, but when checking on ISE 10.1 in the
design summary->Module Level Utilisation I do not see the
slice-breakdown of my single entities. Anyone an idea why I can not see
how much area the different modules in my design contribute to the
overall size?

Thanks

On Jul 8, 8:17*pm, Andi <a...@hotmail.com> wrote:
> Hi
>
> Probably a quite popular question, but when checking on ISE 10.1 in the
> design summary->Module Level Utilisation I do not see the
> slice-breakdown of my single entities. Anyone an idea why I can not see
> how much area the different modules in my design contribute to the
> overall size?
>
> Thanks

need enable "detailed map report"

Antti

>
> need enable "detailed map report"
>
> Antti

Thanks for that Antti. I had a look into the map properties and there I
said

Other map command line options: -detail

According to the command line documentary, this should enable the
detailed map report, however, result is the same... It does not show me
any breakdown

Any other ideas maybe?