Board-level clock phase delay calculation in the fpga board?

In the Altera nios reference design in the cyclone kit,the sdram pll clock
phase shift is -3.5ns.
"This PLL introduces a phase-shift which compensates for board-level delays
in
the clock network.Other boards my require different settings."
I don't know how to calculate the delays on my board.
Could someone tell me the way to calculate the board-level delays?

Thanks and Regards

In article <cm1iol$2c7o$[email protected]>, kingkang <[email protected]> wrote:
>I don't know how to calculate the delays on my board.
>Could someone tell me the way to calculate the board-level delays?

Some DDR designs require a loop on the board equal to the average
bus trace length and then use that to "measure" it.

--
Ben Jackson
<[email protected]>
http://www.ben.com/