FPGA Central

Hi !
Is this possible, to implement function with 4 inputs, 1 output using
also DFFE component with clk, ena and preset signals provided in one Logic
Cell ??
I mean, can code listed below be compiled to use less than 2 cells of
resources ?? I always thought, that controlling signals for latches in Logic
Cells don't increase of resource utility.
SUBDESIGN c_cell
(
clk :INPUT;
ena :INPUT;
reset :INPUT;
c_prev :INPUT;
b[0..1] :INPUT;
a :INPUT;
q :OUTPUT;
)

VARIABLE
q FFE;
BEGIN
q.clk = clk;
q.ena = ena;
q.clrn = reset;
q.d = c_prev $ (a&(b0$b1));
q = q;
END;

"Maciek" <[email protected]> writes:

> Hi !
> Is this possible, to implement function with 4 inputs, 1 output using
> also DFFE component with clk, ena and preset signals provided in one Logic
> Cell ??
> I mean, can code listed below be compiled to use less than 2 cells of
> resources ?? I always thought, that controlling signals for latches in Logic
> Cells don't increase of resource utility.

Hi Maciek,

What device are you targetting?

The older (10K/1K) series don't have dedicated clock enable signals,
or synchronous presets/clears, so they take up one of your inputs
each.

This changed with later devices, eg Apex has dedicated CE inputs for
the LE, and LAB wide synch clear and load signals. The data that is
loaded uses the d3 input still.

Looking at the Cyclone datasheet, it seems to be similar to Apex in
that regard.

Does that help?

Cheers,
Martin

--
[email protected]
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

> Hi Maciek,
>
> What device are you targetting?
>
> The older (10K/1K) series don't have dedicated clock enable signals,
> or synchronous presets/clears, so they take up one of your inputs
> each.
>
> This changed with later devices, eg Apex has dedicated CE inputs for
> the LE, and LAB wide synch clear and load signals. The data that is
> loaded uses the d3 input still.
>
> Looking at the Cyclone datasheet, it seems to be similar to Apex in
> that regard.
>
> Does that help?
>
> Cheers,
> Martin
Hi Martin!
Thank You for Your suggestion about checking the targeting device. I
still don't know how to use AHDL to take advantage of dedicated control
inputs in Apex devices, but I think I will solve this problem soon.
Regards,
Maciek

"Maciek" <[email protected]> wrote in message news:<bj0c04$vn2$[email protected]>...
> Hi !
> Is this possible, to implement function with 4 inputs, 1 output using
> also DFFE component with clk, ena and preset signals provided in one Logic
> Cell ??
> I mean, can code listed below be compiled to use less than 2 cells of
> resources ?? I always thought, that controlling signals for latches in Logic
> Cells don't increase of resource utility.
> SUBDESIGN c_cell
> (
> clk :INPUT;
> ena :INPUT;
> reset :INPUT;
> c_prev :INPUT;
> b[0..1] :INPUT;
> a :INPUT;
> q :OUTPUT;
> )
>
> VARIABLE
> q FFE;
> BEGIN
> q.clk = clk;
> q.ena = ena;
> q.clrn = reset;
> q.d = c_prev $ (a&(b0$b1));
> q = q;
> END;

Hi Maciek,

Change the code as follows :

VARIABLE
my_reg FFE;

Instead of

VARIABLE
q FFE;

my_reg.clk = clk;
.....
.....
q = my_reg.q and it should work (i.e. fit in one Logic Cell).. I
checked it for the APEX, Stratix and Cyclone families.

- Subroto Datta
Altera Corp.

"Maciek" <[email protected]> writes:

> > Hi Maciek,
> >
> > What device are you targetting?
> >
> > The older (10K/1K) series don't have dedicated clock enable signals,
> > or synchronous presets/clears, so they take up one of your inputs
> > each.
> >
> > This changed with later devices, eg Apex has dedicated CE inputs for
> > the LE, and LAB wide synch clear and load signals. The data that is
> > loaded uses the d3 input still.
> >
> > Looking at the Cyclone datasheet, it seems to be similar to Apex in
> > that regard.
> >
> > Does that help?
> >
> > Cheers,
> > Martin
> Hi Martin!
> Thank You for Your suggestion about checking the targeting device. I
> still don't know how to use AHDL to take advantage of dedicated control
> inputs in Apex devices, but I think I will solve this problem soon.

I think (although I'm not an AHDL man myself) that your code ought to
do the right thing, *if* the device you're targetting has a
capability... I've bashed in what I think your HDL is doing as a
schematic (Quartus II 2.2). If you'd like a copy of the file, let me
know by email and I'll send it you.

Targetting a Cyclone device it produces one LUT and a FF:

From the EQN file...
inst_lut_out = c_prev # a & (b0 # b1);
inst = DFFEA(inst_lut_out, GLOBAL(CLK), GLOBAL(RESETn), CKE, , );

Running your AHDL file produced 2 LUTs, as you said, which seems wrong
- I'd open a case with Altera obout it...

Just for completeness, targetting a 1K (Acex) gives:

inst_lut_out = A1L8;
inst = DFFEA(inst_lut_out, GLOBAL(CLK), GLOBAL(RESETn), , CKE, , );
A1L8 = c_prev # a & (b1 # b0);

thereby using two LEs.

It's not easy to see in the floorplanner what's going on, as both
devices claim to be using a DFFE with a clock enable pin, but you
can;t see the way that the 3rd input is being used as that CKE signal
in the 1K architecure. Why do we not have an FPGA Editor for Altera
for tracking these low-level things down...?

Oh well, hope that helps a little!

Cheers,
Martin

--
[email protected]
TRW Conekt, Solihull, UK
http://www.trw.com/conekt