FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > DSP

DSP comp.dsp newsgroup, mailing list

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 02-02-2005, 04:03 PM
quick one
Guest
 
Posts: n/a
Default Zero Padding a DFT

What I meant to ask about crosscorrelation:

Suppose I have 2 signals r[n] and y[n] each of length N, and zero pad them
to double their lengths and compute Y[k]R[k]* using FFTs in matlab. And
then I zero pad that product with 8N zeros BEFORE taking the 10N-IFFT to
get the crosscorrelation.

It seems my correlation results are worse, but I cant understand exactly
why.

any help is appreciated!

This message was sent using the Comp.DSP web interface on DSPRelated.com
Reply With Quote
  #2 (permalink)  
Old 02-02-2005, 04:22 PM
Gordon Sande
Guest
 
Posts: n/a
Default Re: Zero Padding a DFT



quick one wrote:
> What I meant to ask about crosscorrelation:
>
> Suppose I have 2 signals r[n] and y[n] each of length N, and zero pad them
> to double their lengths and compute Y[k]R[k]* using FFTs in matlab. And
> then I zero pad that product with 8N zeros BEFORE taking the 10N-IFFT to
> get the crosscorrelation.
>
> It seems my correlation results are worse, but I cant understand exactly
> why.
>
> any help is appreciated!
>
> This message was sent using the Comp.DSP web interface on DSPRelated.com



The usual technical verbal shorthand (jargon) hides a lot of details.

Zero padding of a time sequence before taking its Fourier transform
is fairly straightforward to describe and understand.

BUT what is zero padding of a sequence of Fourier coefficients? When
done slowly and in full detail the Fourier transformed operation of
zero padding transforms into an interpolation operation which takes
a moderately complicated explanation. Perhaps you need more that
about 1/3 of a jargon filled sentence to say what you intended and
what you did.
Reply With Quote
  #3 (permalink)  
Old 02-02-2005, 04:26 PM
John Smith
Guest
 
Posts: n/a
Default Re: Zero Padding a DFT


Homework season strikes again.... second posting of EXACTLY the same
question. Hmmmmmm.....


Reply With Quote
  #4 (permalink)  
Old 02-02-2005, 04:47 PM
me again
Guest
 
Posts: n/a
Default Re: Zero Padding a DFT

Sorry it was to help understand some results from a lab i did. But I have
already since figured it out on my own! Thanks

This message was sent using the Comp.DSP web interface on DSPRelated.com
Reply With Quote
  #5 (permalink)  
Old 02-02-2005, 05:29 PM
Jerry Avins
Guest
 
Posts: n/a
Default Re: Zero Padding a DFT

me again wrote:

> Sorry it was to help understand some results from a lab i did. But I have
> already since figured it out on my own! Thanks
>
> This message was sent using the Comp.DSP web interface on DSPRelated.com


Please don't keep us in suspense; explain a little.

Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ
Reply With Quote
  #6 (permalink)  
Old 02-02-2005, 05:34 PM
dspchick
Guest
 
Posts: n/a
Default Re: Zero Padding a DFT

yes, this was a last resort to help me understand results of a lab, after
trying to figure this out over the period of a week with no avail. i have
since figured out what was happening! thanks.


This message was sent using the Comp.DSP web interface on DSPRelated.com
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Question about coefficient padding fl FPGA 0 06-18-2008 05:58 PM
Padding strings [email protected] VHDL 5 11-22-2007 12:30 PM
Implicit Zero Padding? Gary Spivey Verilog 8 11-03-2006 06:54 PM
Zero padding and Cross Correlations dspchick DSP 1 02-03-2005 03:52 AM
0-padding in verilog 2001 Jason Zheng Verilog 4 11-26-2004 09:15 PM


All times are GMT +1. The time now is 01:12 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved