FPGA Central

What is the best way (in terms of reduced computation thus resulting i
reduced power consumption) to implement DCT in hardware(iam interested i
doing RTL and then synthesize with some technology library rather tha
doing an FPGA kind of implementation). I intend to implement 8x8 DCT wit
each element having an accuracy of 16 bits

On Nov 14, 8:16 am, "jolly_juggernaut" <kumar...@rediffmail.com>
wrote:
> What is the best way (in terms of reduced computation thus resulting in
> reduced power consumption) to implement DCT in hardware(iam interested in
> doing RTL and then synthesize with some technology library rather than
> doing an FPGA kind of implementation). I intend to implement 8x8 DCT with
> each element having an accuracy of 16 bits

I'm curious. Why not use some prebuilt IP (e.g., Xilinx LogicCore
DCT)? Do you want to execute your DCT on programmable logic devices
from more than one company or in an ASIC?

Darol Klawetter