FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > DSP

DSP comp.dsp newsgroup, mailing list

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-10-2006, 10:45 AM
[email protected]
Guest
 
Posts: n/a
Default Wavelet regularity condition

Hi,

In the following link :
http://perso.wanadoo.fr/polyvalens/c....html#section3

the writer hasn't put the bounds on the integral. Do you know which the
bounds are? In my country I don't have the ability to buy the book that
the writer refers to.

thank you.

Reply With Quote
  #2 (permalink)  
Old 03-10-2006, 12:36 PM
Matthieu Puigt
Guest
 
Posts: n/a
Default Re: Wavelet regularity condition

Hi,

The bounds are -/+ infinity.

For example, you can see it in this paper :
http://cm.bell-labs.com/who/wim/papers/overview.ps

Reply With Quote
  #3 (permalink)  
Old 03-10-2006, 02:17 PM
[email protected]
Guest
 
Posts: n/a
Default Re: Wavelet regularity condition


Matthieu Puigt wrote:
> Hi,
>
> The bounds are -/+ infinity.
>
> For example, you can see it in this paper :
> http://cm.bell-labs.com/who/wim/papers/overview.ps



thank you Matthieu you are great!

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
don't care condition sandi FPGA 2 02-02-2006 07:21 PM
Condition Coverage Using ModelSim arvi FPGA 0 10-26-2005 06:10 PM
while condition Daniel VHDL 7 05-23-2005 04:29 PM
race condition sridhar Verilog 3 04-26-2004 06:57 AM
Re: the skew and race condition Jonathan Bromley FPGA 0 07-01-2003 02:07 PM


All times are GMT +1. The time now is 02:21 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved