FPGA Central

My IF is 5Mhz.I need to reduce my sampling frequency 409.8Mhz to 20.48 Mhz by using FIR lowpass filter, so i am decimating it in 2 stages , first time i am using cic filter and decimation factor 5 then i will get the new sampling frequency 81.9 which is given to half band filter by decimating factor 4 then we will obtain finally 20.48 Mhz.

when we are using cic filter for the first stage of decimation we are using 5 stage

when we are sending the sampling frequency of 81.9 to half band filter and decimate by 4 we will obtain new sampling frequency as 20.48 where pass band is 10Mh and stop band is 15Mhz

i also would like to know which filter will be best suitable for this for decimation... if i am wrong in selecting the filers ..

parameters ; passband is 0.1dB, stop band is 30dB, passband frequency 10Mhz, Stop band 15Mhz.

i need matlab code for this and if possible vhdl code because i need to implement this on vertex 5 board..

many thanks in advances..
it will be great help for me ....

please let me know if any one need any more information...

waiting for reply,

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