FPGA Central

Hai,

To test and verify the FIR filter Wat r all the test inputs as samples
x(n) ....i can apply in addition to the following:
Impulse,step,sine,triangular,sawtooth,rectangular pulse,gaussian white
noise..

1.whether the above test generation signals are sufficient??
2.r still i have to add more???
3.wat r the other corner test cases??

regards,
faz

Dnia 02-06-2008 o 16:25:24 faz <fazulu.vlsi@gmail[email protected]> napisa³(a):

> Hai,
>
> To test and verify the FIR filter Wat r all the test inputs as samples
> x(n) ....i can apply in addition to the following:
> Impulse,step,sine,triangular,sawtooth,rectangular pulse,gaussian white
> noise..
>
> 1.whether the above test generation signals are sufficient??
> 2.r still i have to add more???
> 3.wat r the other corner test cases??
>
> regards,
> faz

A good training will be verifying an apple first.
Can you verify an apple?
I'm serious.

--
Mikolaj

>A good training will be verifying an apple first.
>Can you verify an apple?
>I'm serious.
>
>--
>Mikolaj

Hi Mikolaj,

How does one verify apple??

Maybe Newton used Gravity to Verify Falling Apple....
or was is vice-versa??

And as someone rightly said: An apple a day keeps the
the doctor away and if the doctor is beautiful you
should keep the apple away....

Regards
Bharat Pathak

Arithos Designs
www.Arithos.com

DSP Design Consultancy and Training Company.

On 02-06-2008 at 17:54:26 bharat pathak <[email protected]> wrote:

>
>> A good training will be verifying an apple first.
>> Can you verify an apple?
>> I'm serious.
>>
>> --
>> Mikolaj
>
> Hi Mikolaj,
>
> How does one verify apple??
>
(...)

This is a just question to *faz*.
And this is also his answer.

--
Mikolaj

On Jun 2, 2:04 pm, Mikolaj <sterowanie_komputer...@hahapoczta.onet.pl>
wrote:
> On 02-06-2008 at 17:54:26 bharat pathak <bha...@arithos.com> wrote:
>
>
>
> >> A good training will be verifying an apple first.
> >> Can you verify an apple?
> >> I'm serious.
>
> >> --
> >> Mikolaj
>
> > Hi Mikolaj,
>
> > How does one verify apple??
>
> (...)
>
> This is a just question to *faz*.
> And this is also his answer.
>

what is this? some kinda insider point? or inside joke?

i test FIRs by using MATLAB or Octave to FFT the impulse response to
make sure the frequency response is what i was aiming for.

if you mean testing the real-time computation, then i dunno what the
answer is. general FIRs are pretty simple and straight-forward.
("fast convolution" ain't so simple.) it's pretty easy to calculate
what the largest possible output sample could be, so you can have an
idea for how to scale your FIR coefs.

r b-j

On 02-06-2008 at 23:35:42 robert bristow-johnson
<[email protected]> wrote:

(...)

It seems you would be able to verify an apple.
Let's wait till tomorrow. Let's wait for 'faz'.
If he would manage to verify an apple
he would be able to verify enything.
He even would be able to verify such words as:
to verify, optimal, best, how and why.

--
Mikolaj

On 2 Jun, 23:35, robert bristow-johnson <r...@audioimagination.com>
wrote:
> On Jun 2, 2:04 pm, Mikolaj <sterowanie_komputer...@hahapoczta.onet.pl>
> wrote:
>
>
>
>
>
> > On 02-06-2008 at 17:54:26 bharat pathak <bha...@arithos.com> wrote:
>
> > >> A good training will be verifying an apple first.
> > >> Can you verify an apple?
> > >> I'm serious.
>
> > >> --
> > >> Mikolaj
>
> > > Hi Mikolaj,
>
> > > * *How does one verify apple??
>
> > (...)
>
> > This is a just question to *faz*.
> > And this is also his answer.
>
> what is this? *some kinda insider point? *or inside joke?

Nah, probably frustration or something like that. This guy
'faz' has asked the same question with minor variations for
a few days now, without showing evidence that he actually
contemplates the responses.

Rune

Can u please make a comment on watever work i am doing and suggest for
the same...


This guy
'faz' has asked the same question with minor variations for
a few days now

I am helpless i am unable to get proper answer i even tried books and
various resources


Mikolaj wrote:
> On 02-06-2008 at 23:35:42 robert bristow-johnson
> <[email protected]> wrote:
>
> (...)
>
> It seems you would be able to verify an apple.
> Let's wait till tomorrow. Let's wait for 'faz'.
> If he would manage to verify an apple
> he would be able to verify enything.
> He even would be able to verify such words as:
> to verify, optimal, best, how and why.
>
> --
> Mikolaj

On 03-06-2008 at 06:45:15 faz <[email protected]> wrote:

> Can u please make a comment on watever work i am doing and suggest for
> the same...
>
(...)

Step by step. How would you verify an apple?

--
Mikolaj

Step by step. How would you verify an apple?
I am already confused and i dont know wat your r trying to explain
here..

On Jun 3, 12:31*pm, Mikolaj
<sterowanie_komputer...@hahapoczta.onet.pl> wrote:
> On 03-06-2008 at 06:45:15 faz <fazulu.v...@gmail.com> wrote:
>
> > Can u please make a comment on watever work i am doing and suggest for
> > the same...
>
> (...)
>
> Step by step. How would you verify an apple?
>
> --
> Mikolaj

On 03-06-2008 at 13:53:15 faz <[email protected]> wrote:

> Step by step. How would you verify an apple?
> I am already confused and i dont know wat your r trying to explain
> here..

And I'm confused about your "how to verify FIR" question.
How to verify FIR is exactly the same as to verify an apple.

It will be extremely long way.
Start with usenet netiquette.
http://www.cs.tut.fi/~jkorpela/usenet/dont.html


--
Mikolaj

Mikolaj wrote:
> On 03-06-2008 at 13:53:15 faz <[email protected]> wrote:
>
>> Step by step. How would you verify an apple?
>> I am already confused and i dont know wat your r trying to explain
>> here..
>
> And I'm confused about your "how to verify FIR" question.
> How to verify FIR is exactly the same as to verify an apple.
>
> It will be extremely long way.
> Start with usenet netiquette.
> http://www.cs.tut.fi/~jkorpela/usenet/dont.html

It's a language problem. give him a break.

Faz: You need to specify what you mean by "verify". "Verify" could mean
any one of several things, or a combination of them.
1. Is it really an FIR filter?
2. Does the filter behave according to the design? (is the code good)?
3. Is the filter's impulse response correct (is the design good)?
4. Will the worst-case signal cause the filter to saturate?

I assume that you mean "verify proper performance".

Start with two tests:
1. Feed the filter with all zero samples. The output should be all zero.
2. Change one of those zeros to a one, The output should be the filter's
coefficients.

Then check for overflow.
3. Feed the filter with all maximum values, setting the sign sequence to
the same as the filter coefficients. One output samples will be the
sum of the coefficient's absolute values, times the maximum input
value. If that doesn't overflow, you're set.

Jerry
--
Engineering is the art of making what you want from things you can get.
?????????????????????????????????????????????????? ?????????????????????

1. Is it really an FIR filter?
Yes it is a FIR filter
2. Does the filter behave according to the design? (is the code
good)?
3. Is the filter's impulse response correct (is the design good)?
I have done impulse test all the coefficients are coming out properly

4. Will the worst-case signal cause the filter to saturate?
I dont know wat this means

Feed the filter with all maximum values, setting the sign sequence to
the same as the filter coefficients

I will do this test..by the way feeding with maximum value should be
same as maximum value in filter coefficients??

Thanks for your suggestions....

regards,
faz



Jerry Avins wrote:
> Mikolaj wrote:
> > On 03-06-2008 at 13:53:15 faz <[email protected]> wrote:
> >
> >> Step by step. How would you verify an apple?
> >> I am already confused and i dont know wat your r trying to explain
> >> here..
> >
> > And I'm confused about your "how to verify FIR" question.
> > How to verify FIR is exactly the same as to verify an apple.
> >
> > It will be extremely long way.
> > Start with usenet netiquette.
> > http://www.cs.tut.fi/~jkorpela/usenet/dont.html
>
> It's a language problem. give him a break.
>
> Faz: You need to specify what you mean by "verify". "Verify" could mean
> any one of several things, or a combination of them.
> 1. Is it really an FIR filter?
> 2. Does the filter behave according to the design? (is the code good)?
> 3. Is the filter's impulse response correct (is the design good)?
> 4. Will the worst-case signal cause the filter to saturate?
>
> I assume that you mean "verify proper performance".
>
> Start with two tests:
> 1. Feed the filter with all zero samples. The output should be all zero.
> 2. Change one of those zeros to a one, The output should be the filter's
> coefficients.
>
> Then check for overflow.
> 3. Feed the filter with all maximum values, setting the sign sequence to
> the same as the filter coefficients. One output samples will be the
> sum of the coefficient's absolute values, times the maximum input
> value. If that doesn't overflow, you're set.
>
> Jerry
> --
> Engineering is the art of making what you want from things you can get.
> ?????????????????????????????????????????????????? ?????????????????????

faz wrote:
> 1. Is it really an FIR filter?
> Yes it is a FIR filter

I didn't mean to ask. It was a suggestion for what to do.

> 2. Does the filter behave according to the design? (is the code
> good)?
> 3. Is the filter's impulse response correct (is the design good)?
> I have done impulse test all the coefficients are coming out properly

That's most of it. Have you verified that the impulse response has the
correct response?

> 4. Will the worst-case signal cause the filter to saturate?
> I dont know wat this means

It means:
> Feed the filter with all maximum values, setting the sign sequence to
> the same as the filter coefficients
>
> I will do this test..by the way feeding with maximum value should be
> same as maximum value in filter coefficients??

It should be the largest sample you will apply. Usually, full scale.

> Thanks for your suggestions....

You're welcome.

Jerry
--
Engineering is the art of making what you want from things you can get.

On 03-06-2008 at 15:56:58 Jerry Avins <[email protected]> wrote:


> It's a language problem. give him a break.
(...)

I don't think so. It's a general understanding problem.
I was trying to show him a way but it is useless.
He is just asking and not answering.
He's acting entirely blindly.

--
Mikolaj

On Jun 3, 12:07*pm, Jerry Avins <j...@ieee.org> wrote:
> faz wrote:
> > 1. Is it really an FIR filter?
> > Yes it is a FIR filter
>
> I didn't mean to ask. It was a suggestion for what to do.
>
> > *2. Does the filter behave according to the design? (is the code
> > good)?
> > *3. Is the filter's impulse response correct (is the design good)?
> > I have done impulse test all the coefficients are coming out properly
>
> That's most of it. Have you verified that the impulse response has the
> correct response?
>
> > *4. Will the worst-case signal cause the filter to saturate?
> > I dont know wat this means
>
> It means:
>
> > Feed the filter with all maximum values, setting the sign sequence to
> > * * *the same as the filter coefficients

Jerry,

Shouldn't these data signs be in reverse order of the coefficient
signs if they are being fed in?

Dirk
>
> > I will do this test..by the way feeding with maximum value should be
> > same as maximum value in filter coefficients??
>
> It should be the largest sample you will apply. Usually, full scale.
>
> > Thanks for your suggestions....
>
> You're welcome.
>
> Jerry
> --
> Engineering is the art of making what you want from things you can get.

dbell wrote:
> On Jun 3, 12:07 pm, Jerry Avins <j...@ieee.org> wrote:

...

>> It means:
>>
>>> Feed the filter with all maximum values, setting the sign sequence to
>>> the same as the filter coefficients
>
> Jerry,
>
> Shouldn't these data signs be in reverse order of the coefficient
> signs if they are being fed in?
>
> Dirk

Yes. To keep the explanation as simple as I believe the problem is, I
assumed a symmetrical filter and a lack of interest in the sign of the
result. Thank you for making the condition explicit.

...

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

Mikolaj wrote:
> On 03-06-2008 at 15:56:58 Jerry Avins <[email protected]> wrote:
>
>
>> It's a language problem. give him a break.
> (...)
>
> I don't think so. It's a general understanding problem.
> I was trying to show him a way but it is useless.
> He is just asking and not answering.
> He's acting entirely blindly.

So let's give him the tools to prove you right.

Jerry
--
Engineering is the art of making what you want from things you can get.
?????????????????????????????????????????????????? ?????????????????????

On 03-06-2008 at 20:51:33 Jerry Avins <[email protected]> wrote:

> Mikolaj wrote:
>> On 03-06-2008 at 15:56:58 Jerry Avins <[email protected]> wrote:
>>
>>> It's a language problem. give him a break.
>> (...)
>> I don't think so. It's a general understanding problem.
>> I was trying to show him a way but it is useless.
>> He is just asking and not answering.
>> He's acting entirely blindly.
>
> So let's give him the tools to prove you right.
>
> Jerry

But he is not willing to co-operate.
I think he don't want to understand,
don't want to learn, don't want to read
and don't want to talk.
He didn't read the netiquette, this is one example.
He is trying to verify an apple
an does not see anything strange with that.


--
Mikolaj

But he is not willing to co-operate.

Without learning resources i am not blindly designing a FIR
filter...do u think it is possible...Might be my understanding is not
to the maximum level as u r excepting as i am new to dsp..I have been
updating till i reach that level...can u share some links,good
resources about the FIR filter design and verification...

Let me clear u first wat i have done so far...Before designing i red
all the FAQ of this groups about FIR filter design and followed by
other resources in the net.Even i refered books like discrete time
signal processing,digital filter designers handbook and practical
analog and digital filter design(if u knew some more books send the
link of the same).Then decided to design a FIR filter to that can
support upto 256 taps and generated the coefficients using equiripple
design method with direct form 1 structure using the FDA tool of
MATLAB.

I have done systemverilog coding for implementing the design in
FPGA...for that i will take coefficients and input samples generated
from MATLAB as inputs to the filter and compute the response...

To verify it i have done impulse test and checked in the simulation
all the coefficients are coming out...As suggested by jerry i will be
doing overflow test before implementing the design in FPGA...And i
asked this group to knew if there r other test cases to make my design
more perfect...

I think i explained from my side...Is it clear to u...give your
comments and suggestions


On Jun 4, 2:00*am, Mikolaj <sterowanie_komputer...@hahapoczta.onet.pl>
wrote:
> On 03-06-2008 at 20:51:33 Jerry Avins <j...@ieee.org> wrote:
>
> > Mikolaj wrote:
> >> On 03-06-2008 at 15:56:58 Jerry Avins <j...@ieee.org> wrote:
>
> >>> It's a language problem. give him a break.
> >> (...)
> >> *I don't think so. It's a general understanding problem.
> >> I was trying to show him a way but it is useless.
> >> He is just asking and not answering.
> >> He's acting entirely blindly.
>
> > So let's give him the tools to prove you right.
>
> > Jerry
>
> But he is not willing to co-operate.
> I think he don't want to understand,
> don't want to learn, don't want to read
> and don't want to talk.
> He didn't read the netiquette, this is one example.
> He is trying to verify an apple
> an does not see anything strange with that.
>
> --
> Mikolaj

On 04-06-2008 at 06:35:16 faz <[email protected]> wrote:

I beg you, please, read the usenet netiquette.

> But he is not willing to co-operate.
>
> Without learning resources i am not blindly designing a FIR
> filter...do u think it is possible...Might be my understanding is not
> to the maximum level as u r excepting as i am new to dsp..I have been
> updating till i reach that level...can u share some links,good
> resources about the FIR filter design and verification...

Yes, I think you have no idea what you are doing.
You just blindly use software that generates some numbers
and you are trying to verify those numbers (coefficients)
to find if they are perfect.
I asked you earlier, what do you mean writing "optimal" or "perfect"?

To verify if an apple is "sweet" we can use tongue sensor
and "bite" method and compare sweetness with our memory
and experience.
We can verify another "property" of an apple, the colour.
To verify if an apple is "red" we ca use eye sensor but
we have to excite an apple with white light and then tak an eye
measurement.
Then compare results to our brain standard for "red".

To verify means to compare what we have to what we want.
What do *you* want from your numbers? What is your goal?
What would you like to achieve?
What "property" of of a filter is important in your design?
Is it attenuation in bandpass or in stopband, maybe delay
or accuracy or maybe overshoot in step response or response time or
many many else properties and their combinations?


> Let me clear u first wat i have done so far...Before designing i red
> all the FAQ of this groups about FIR filter design and followed by
> other resources in the net.Even i refered books like discrete time
> signal processing,digital filter designers handbook and practical
> analog and digital filter design(if u knew some more books send the
> link of the same).Then decided to design a FIR filter to that can
> support upto 256 taps and generated the coefficients using equiripple
> design method with direct form 1 structure using the FDA tool of
> MATLAB.

Reading FAQ is useless when you don't understand bases.


(...)



--
Mikolaj

I beg you, please, read the usenet netiquette.
Reading FAQ is useless when you don't understand bases.

Dont worry i red that...It is the first point mentioned..

You just blindly use software that generates some numbers
and you are trying to verify those numbers (coefficients)
to find if they are perfect.

Yes you r correct...its not my headache...I am just doing the MAC
operation to implement a generic FIR filter whose response entirely
depended on the way the filter designer generated the
coefficients(watever property of the filter u r talking about)...
accepting constraints from the digital filter designers(people like u)
i will do response checks for any type of FIR filter(LP.HP,BP,BR) like
verifying an apple ...so i depended on software tool..but at the same
time u cannot blame those software tools which will make the job
easier for people like me.


What do *you* want from your numbers? What is your goal?
What would you like to achieve?
What "property" of of a filter is important in your design?

Again i am behind how much resources on the FPGA will be utlized at
the maximum extend,maximum clock requirement,computation time and
critical path delay these are the properties which i am working on
it...

if u knew some more books send the link of the same..
Surely now i got interest to learn about the design more than
implementing it so that i can answer all your questions but alas you r
not given a reply for the resources which i asked you...

regards,
faz


On Jun 4, 11:40*am, Mikolaj
<sterowanie_komputer...@hahapoczta.onet.pl> wrote:
> On 04-06-2008 at 06:35:16 faz <fazulu.v...@gmail.com> wrote:
>
> I beg you, please, read the usenet netiquette.
>
> > But he is not willing to co-operate.
>
> > Without learning resources i am not blindly designing a FIR
> > filter...do u think it is possible...Might be my understanding is not
> > to the maximum level as u r excepting as i am new to dsp..I have been
> > updating till i reach that level...can u share some links,good
> > resources about the FIR filter design and verification...
>
> Yes, I think you have no idea what you are doing.
> You just blindly use software that generates some numbers
> and you are trying to verify those numbers (coefficients)
> to find if they are perfect.
> I asked you earlier, what do you mean writing "optimal" or "perfect"?
>
> To verify if an apple is "sweet" we can use tongue sensor
> and "bite" method and compare sweetness with our memory
> and experience.
> We can verify another "property" of an apple, the colour.
> To verify if an apple is "red" we ca use eye sensor but
> we have to excite an apple with white light and then tak an eye *
> measurement.
> Then compare results to our brain standard for "red".
>
> To verify means to compare what we have to what we want.
> What do *you* want from your numbers? What is your goal?
> What would you like to achieve?
> What "property" of of a filter is important in your design?
> Is it attenuation in bandpass or in stopband, maybe delay
> or accuracy or maybe overshoot in step response or response time or
> many many else properties and their combinations?
>
> > Let me clear u first wat i have done so far...Before designing i red
> > all the FAQ of this groups about FIR filter design and followed by
> > other resources in the net.Even i refered books like discrete time
> > signal processing,digital filter designers *handbook and practical
> > analog and digital filter design(if u knew some more books send the
> > link of the same).Then decided to design a FIR filter to that can
> > support upto 256 taps and generated the coefficients using equiripple
> > design method with direct form 1 structure using the FDA tool of
> > MATLAB.
>
> Reading FAQ is useless when you don't understand bases.
>
> (...)
>
> --
> Mikolaj

On 04-06-2008 at 10:47:02 faz <[email protected]> wrote:

> I beg you, please, read the usenet netiquette.
> Reading FAQ is useless when you don't understand bases.
>
> Dont worry i red that...It is the first point mentioned..

Then why don't you follow the rules of netiquette?

In my view you should ask those filter designers
who gave you the coefficients about what performance parameters
they are expecting. The kind of test depend on this parameters.
If the parameter to verify is an overshoot then you will perform a step
response.
When the parameter of interst is bandwith then you will perform a
frequency spectrum analysis.

If there was no instruction about what kind of parameter to verify
then you can test anything you want (Infinite number
of input signals and their responses) because you are not verifying but
making a series of tests then. Do it as long as they will be pleased.


> Surely now i got interest to learn about the design more than
> implementing it so that i can answer all your questions but alas you r
> not given a reply for the resources which i asked you...

Well, you didn't specify erlier that you are interested in
FPGA implementation and not in filter design and signal processing.
All the time we are trying to determine what your "question" is
because you asked to generally and so the answer would be "any recourses
you want".


--
Mikolaj