FPGA Central

hello everyone...

my questions are related to k=7 rate=1/2 decoder and i am thinking o
implementing it on FPGA using VHDL.....a general solution will also b
appreciated.

first question..for 3 bit soft-decision coding is it the encoder tha
encodes 1 input to 2 3-bit encoded outputs or is it the reciever befor
viterbi decoder that quantizes the recieved encoded value to 2 3-bi
encoded values.....i think it is the reciever...what do you say...

second question....if the answer to the first question is reciever the
for soft bit decision how do we generate a two 3-bit expected value(tota
six bit) for the state transition of the encoder at the reciver side whil
at the trasnmitter side we only generated two 1-bit (total 2 bit)output
for state transition...

third question..how do we calculate metric for soft decision.....and wha
is soft-bit's impact on path metric and branch metric units of a viterb
decoder.....

On Mar 22, 6:18 am, "khurram712" <khurram...@hotmail.com> wrote:
> hello everyone...
>
> my questions are related to k=7 rate=1/2 decoder and i am thinking of
> implementing it on FPGA using VHDL.....a general solution will also be
> appreciated.
>
> first question..for 3 bit soft-decision coding is it the encoder that
> encodes 1 input to 2 3-bit encoded outputs or is it the reciever before
> viterbi decoder that quantizes the recieved encoded value to 2 3-bit
> encoded values.....i think it is the reciever...what do you say...
>
> second question....if the answer to the first question is reciever then
> for soft bit decision how do we generate a two 3-bit expected value(total
> six bit) for the state transition of the encoder at the reciver side while
> at the trasnmitter side we only generated two 1-bit (total 2 bit)outputs
> for state transition...
>
> third question..how do we calculate metric for soft decision.....and what
> is soft-bit's impact on path metric and branch metric units of a viterbi
> decoder.....


This is interesting. If you look at a thread
with title 'qpsk viterbi decoding', the poster
is asking exactly the same question.

Do you guys happen to be working for the same
company, competing companies, or the same design
project? ;-)

Hope that helps,
Julius

On Mar 22, 5:08 pm, "julius" <juli...@gmail.com> wrote:
> On Mar 22, 6:18 am, "khurram712" <khurram...@hotmail.com> wrote:
>
>
>
> > hello everyone...
>
> > my questions are related to k=7 rate=1/2 decoder and i am thinking of
> > implementing it on FPGA using VHDL.....a general solution will also be
> > appreciated.
>
> > first question..for 3 bit soft-decision coding is it the encoder that
> > encodes 1 input to 2 3-bit encoded outputs or is it the reciever before
> > viterbi decoder that quantizes the recieved encoded value to 2 3-bit
> > encoded values.....i think it is the reciever...what do you say...
>
> > second question....if the answer to the first question is reciever then
> > for soft bit decision how do we generate a two 3-bit expected value(total
> > six bit) for the state transition of the encoder at the reciver side while
> > at the trasnmitter side we only generated two 1-bit (total 2 bit)outputs
> > for state transition...
>
> > third question..how do we calculate metric for soft decision.....and what
> > is soft-bit's impact on path metric and branch metric units of a viterbi
> > decoder.....
>
> This is interesting. If you look at a thread
> with title 'qpsk viterbi decoding', the poster
> is asking exactly the same question.
>
> Do you guys happen to be working for the same
> company, competing companies, or the same design
> project? ;-)
>
> Hope that helps,
> Julius


Nevermind, I should have thought that some people
like to start multiple threads on basically the
same question.

Julius

julius wrote:

...

> Nevermind, I should have thought that some people
> like to start multiple threads on basically the
> same question.

That's a very stupid thing to do because it means that answers to the
question will be in different places without cross fertilization. Asking
twice is an example of a stupid question. Stupid questions do exist! :-)

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

julius wrote:
> On Mar 22, 6:18 am, "khurram712" <khurram...@hotmail.com> wrote:
>> hello everyone...
>>
>> my questions are related to k=7 rate=1/2 decoder and i am thinking of
>> implementing it on FPGA using VHDL.....a general solution will also be
>> appreciated.
>>
>> first question..for 3 bit soft-decision coding is it the encoder that
>> encodes 1 input to 2 3-bit encoded outputs or is it the reciever before
>> viterbi decoder that quantizes the recieved encoded value to 2 3-bit
>> encoded values.....i think it is the reciever...what do you say...
>>
>> second question....if the answer to the first question is reciever then
>> for soft bit decision how do we generate a two 3-bit expected value(total
>> six bit) for the state transition of the encoder at the reciver side while
>> at the trasnmitter side we only generated two 1-bit (total 2 bit)outputs
>> for state transition...
>>
>> third question..how do we calculate metric for soft decision.....and what
>> is soft-bit's impact on path metric and branch metric units of a viterbi
>> decoder.....
>
>
> This is interesting. If you look at a thread
> with title 'qpsk viterbi decoding', the poster
> is asking exactly the same question.
>
> Do you guys happen to be working for the same
> company, competing companies, or the same design
> project? ;-)

Sitting in the same lecture theatre? :-)

Steve