Guenter Dannoritzer <
[email protected]> wrote in message news:<c6pb6o$pof$07$
[email protected]>...
> Hello,
>
> I am working on a self-study project and try to implement a DMT
> transmitter in VHDL. This is the first time I am dealing with
> fixed-point implementation of a DSP algorithm. One of the blocks is an
> IFFT which outputs the time domain signal. At the end this signal is
> passed to an ADC, which has at the most a precision of 16-bit.
>
> My question is now whether I should scale my data at the input to the
> IFFT and use an IFFT that outputs already only 16-bit or is it better to
> calculate the IFFT with full precision and then scale the output to the
> 16-bit?
>
> I am kind of lost in what effort I should take to determine how
> significant the error difference between the two ways of implementation
> and a floating point implementation is.
>
> What is a common practice of doing this?
>
>
> Thanks for the help.
>
> Guenter
The answer depends on the internal behavior of the fft/ifft.
The fft "block" may take care of overflow protection for you. This is
a common option for fixed point ffts. If that is the case, then you
need not perform any scaling if the input is 16 bit. The fft routine
will scale down by one bit for each power of two.
If the fft routine does not scale at each stage, then ...
If the internals of the fft are sufficiently large, scale afterwards.
If the internals of the fft cannot handle more than 16 bits, you must
scale before.
-- Mark Borgerding