FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > DSP

DSP comp.dsp newsgroup, mailing list

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 05-19-2004, 10:59 PM
Allis
Guest
 
Posts: n/a
Default Real-Time Workshop Code Optimization

Hi,

I am currently looking at my options in regards to converting some
Matlab code into C. I know that Real-Time Workshop will do this for
me (because this code will eventually be used in an embedded system)
but what concerns me is the optimization level of the code after
Real-Time Workshop is finished.

I have heard that Real-Time Workshop generates clunky, very slow
stand-alone C. I need this code to run quickly due to the constraints
on my system.

If I do not use Real-Time Workshop on this effort, it looks like I
will be converting the code myself into C.

Does anyone have experience with the optimization that Real-Time
Workshop is capable of? Is the resulting code readable? cryptic?
optimized?

Any help would be great.
Thanks!
Allis
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
optimization of vhdl code ashu VHDL 1 05-24-2006 08:20 AM
problem in optimization of vhdl code ashu VHDL 4 05-10-2006 02:16 PM
optimization of vhdl code ashu VHDL 5 05-09-2006 09:12 PM
Is there a quick, not much processing time needed, way to make the same volume on a 16 signed int stream in real time? SA Dev DSP 17 02-26-2004 08:47 PM
Request for Real Digital Real-time Hardware Synth Radium DSP 2 12-31-2003 07:01 AM


All times are GMT +1. The time now is 01:58 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved