FPGA Central

I am developing a DSPC6713B board with one chip of CPLD. The Timer an
general purpose IO programs work normally. The input clock to the DSP CLKI
pin is 25MHz and dsp works on the frequency of 200MHz.

When reset the DSP, the frequency of ECLKOUT,CLKOUT3, CLKOUT2 signal i
correct as the datasheet suggets. The frequency of ECLKOUT signal is CLKI
divided by 2 and CLKOUT3,CLKOUT2 is divided by 8. Everything seem
perfect.

But SDRAM can't be written. A 32-bit SDRAM with 4 banks is connected t
the CE0.THE ECLKOUT signal is set to 80MHz(one fifth of 400MHz) ultilizin
the PLL intialization programs. BUT the ECLKOUT signal turns out to be ver
strange. When Eclkout frequency is about 20MHz, the ECLKOUT signal wave i
a sinusoidal with the amplitude of about 3V, the minimum voltage of signa
is about 0.4V. As the ECLKOUT frequency increases to 50MHz, it is still
sinusoidal wave, but the amplitude decreases to about 0.4V, the minimu
voltage is about 1.2V, that is, there exists more or less a 1.2v DC offse
in the ECLKOUT signal.

The dsp core supply voltage maintains at the level of 1.19V. It is th
same for the ECLKOUT signal if I seperated the DSP and SDRAM. BTW, th
signal is tested by a oscilloscope with bandwidth of 60MHz(200MSa/s). Ther
are no differences for the ECLKOUT signal with a different oscilloscop
with bandwidth of 100MHz(200MSa/s).

Any suggestion would be greated appreciated~~~~