FPGA Central

Hello all,

I work with ADSP21161N... my research is about Active Noise Control..
I'll try explain my problem...

I've a file, with the samples (160 samples - 48Khz of sample frequency) o
a 300hz signal, I use that file and circular buffer to generate the signal
and than I send that signal to the output...

My project is similiar a example SIMD_FIR in analog device site... I'
using a FIR and LMS, algorithms... so, my problem is.. when I run th
algorithm using SISD everything work... but when I try to run the algorith
with SIMD, my signal(300hz) leaves with a noise...

I'll put my algorithms here... SISD and SIMD... just the important as
file...

Really thank's !!!

Henrique L. Barcellos



//************************************************** ****************************
//************************************************** ****************************
//************************************************** ****************************
//FIR_SISD.ASM
//************************************************** ****************************
#include "def21161.h"

#define FILTER_TAPS 200
#define ONEHALF_FILTER_TAPS 100
#define SAMPLES 160
#define mu 0.00001
#define IERROR 2000

/*---------------------------------------------------------------------------*/

.segment /dm dm_data;
.ALIGN 2;
.VAR x[FILTER_TAPS];
.ALIGN 2;
.VAR sinal[SAMPLES] = "sinal_300hz.dat";

.endseg;

/*---------------------------------------------------------------------------*/

.segment /pm pm_data;
.ALIGN 2;
.VAR w[FILTER_TAPS];
.ALIGN 2;
.VAR erro[IERROR];

.endseg;

/*---------------------------------------------------------------------------*/

.segment /pm pm_code;
.GLOBAL init_fir_filter;
.GLOBAL fir;

.EXTERN RX_left_flag;
.EXTERN Left_Channel_In1;
.EXTERN Right_Channel_In1;
.EXTERN Left_Channel_Out0;
.EXTERN Right_Channel_Out0;

init_fir_filter:
b0 = x; l0 = @x;
b1 = sinal; l1 = @sinal;
m1 = 1; m2 = -1; m3 = 2;

b9 = w; l9 = @w;
b11 = error; l11 = @error;
b8 = b9; l8 = l9;
m9 = 2; m10=1;
r12 = 0; f7 = mu;

lcntr=FILTER_TAPS, do clear until lce;
clear: dm(i0,m1)=r12, pm(i9,m10)=r12;

rts;
init_fir_filter.end:


fir:
/* process Signal Input */
f0 = dm(i1,m1);
r2 = 31;
r3 = fix f0 by r2;
DM(Left_Channel_Out0) = r3;

/* process Left Channel Input */
r2 = -31;
r1 = DM(Left_Channel_In1);
f1 = float r1 by r2 ;

dm(i0,m1)=f0, f4 = pm(i9,m10);

f8=f0*f4, f0=dm(i0,m1), f4=pm(i9,m10);
f12=f0*f4, f0=dm(i0,m1), f4=pm(i9,m10);

lcntr= FILTER_TAPS - 3, do macloop until lce;
macloop: f12=f0*f4, f8=f8+f12, f0=dm(i0,m1), f4=pm(i9,m10);
f12=f0*f4, f8=f8+f12;
f13=f8+f12;

f6 = f1 - f13;
pm(i11,m10) = f6;
f1 = f6*f7, f4=dm(i0,m1);
f0 = f1*f4, f12=pm(i9,m10);

lcntr = FILTER_TAPS-1, do update_weights until lce;
f8=f0+f12, f4=dm(i0,m1), f12=pm(i9,m10);
update_weights: f0=f1*f4, pm(i8,m10)=f8;
f8=f0+f12, s0=dm(i0,m2);
main_fir: pm(i8,m10)=f8;

r2 = 31;
r6 = fix f6 by r2;
DM(Right_Channel_Out0) = r6;

rts;
fir.end:

.endseg;



//************************************************** ****************************
//************************************************** ****************************
//************************************************** ****************************
//FIR_SIMD.ASM
//************************************************** ****************************
#include "def21161.h"

#define FILTER_TAPS 200
#define ONEHALF_FILTER_TAPS 100
#define SAMPLES 160
#define mu 0.00001
#define IERROR 2000

/*---------------------------------------------------------------------------*/

.segment /dm dm_data;
.ALIGN 2;
.VAR x[FILTER_TAPS];
.ALIGN 2;
.VAR sinal[SAMPLES] = "sinal_300hz.dat";

.endseg;

/*---------------------------------------------------------------------------*/

.segment /pm pm_data;
.ALIGN 2;
.VAR w[FILTER_TAPS];
.ALIGN 2;
.VAR erro[IERROR];

.endseg;

/*---------------------------------------------------------------------------*/

.segment /pm pm_code;
.GLOBAL init_fir_filter;
.GLOBAL fir;

.EXTERN RX_left_flag;
.EXTERN Left_Channel_In1;
.EXTERN Right_Channel_In1;
.EXTERN Left_Channel_Out0;
.EXTERN Right_Channel_Out0;

init_fir_filter:
b0 = x; l0 = @x;
b1 = sinal; l1 = @sinal;
m1 = 1; m2 = -1; m3 = 2;

b9 = w; l9 = @w;
b11 = error; l11 = @error;
b8 = b9; l8 = l9;
m9 = 2; m10=1;
r12 = 0; f7 = mu;

lcntr=FILTER_TAPS, do clear until lce;
clear: dm(i0,m1)=r12, pm(i9,m10)=r12;

rts;
init_fir_filter.end:


fir:
/* process Signal Input */
f0 = dm(i1,m1);
r2 = 31;
r3 = fix f0 by r2;
DM(Left_Channel_Out0) = r3;

/* process Left Channel Input */
r2 = -31;
r1 = DM(Left_Channel_In1);
f1 = float r1 by r2 ;

/****************** SIMD ******************/

s0 = dm(i0, m1);
bit set MODE1 PEYEN;
s0 = dm(i0, m2);

dm(i0,m3)=f0, f4 = pm(i9,m9);

f8=f0*f4, f0=dm(i0,m3), f4=pm(i9,m9);
f12=f0*f4, f0=dm(i0,m3), f4=pm(i9,m9);

lcntr= ONEHALF_FILTER_TAPS - 3, do macloop until lce;
macloop: f12=f0*f4, f8=f8+f12, f0=dm(i0,m3), f4=pm(i9,m9);
f12=f0*f4, f8=f8+f12;
f8=f8+f12;
r12=s8;
bit clr MODE1 PEYEN;
f13=f8+f12;

/************** END SIMD ******************/

f6 = f1 - f13;
pm(i11,m10) = f6;
f1 = f6*f7, f4=dm(i0,m1);
f0 = f1*f4, f12=pm(i9,m10);

lcntr = FILTER_TAPS-1, do update_weights until lce;
f8=f0+f12, f4=dm(i0,m1), f12=pm(i9,m10);
update_weights: f0=f1*f4, pm(i8,m10)=f8;
f8=f0+f12, s0=dm(i0,m2);
main_fir: pm(i8,m10)=f8;

r2 = 31;
r6 = fix f6 by r2;
DM(Right_Channel_Out0) = r6;

rts;
fir.end:

.endseg;

I have a doubt about whether this method is feasible in general. The
critical question that you have to ask is about the delay between
input and output. First, from hardware standpoint, do you have any
measure about the delay of ADC->CPU->Interrupt call -> Processing ->
Output interrupt -> DAC? I guess the whole path will cost you at least
a few milliseconds. It means that even your DSP does nothing, an input
point will travel a few milliseconds to get sent out. Then you are
using a 200 tap FIR. The delay equals another 100 samples points.

With such a delay, any control in time domain, with the bandwidth that
you asked for, will ends up instable. In the other words, the device
can't control anything at such bandwidth.

It might be a good idea if you go back to your supervisor, if the task
was assigned by him, and discuss the basics of control theory with
him.

James
www.go-ci.com

DigitalSignal wrote:
> I have a doubt about whether this method is feasible in general. The
> critical question that you have to ask is about the delay between
> input and output. First, from hardware standpoint, do you have any
> measure about the delay of ADC->CPU->Interrupt call -> Processing ->
> Output interrupt -> DAC? I guess the whole path will cost you at least
> a few milliseconds. It means that even your DSP does nothing, an input
> point will travel a few milliseconds to get sent out. Then you are
> using a 200 tap FIR. The delay equals another 100 samples points.
>
> With such a delay, any control in time domain, with the bandwidth that
> you asked for, will ends up instable. In the other words, the device
> can't control anything at such bandwidth.
>
> It might be a good idea if you go back to your supervisor, if the task
> was assigned by him, and discuss the basics of control theory with
> him.

Better yet, suggest that the supervisor read Wescott's book. :-)

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

>DigitalSignal wrote:
>> I have a doubt about whether this method is feasible in general. The
>> critical question that you have to ask is about the delay between
>> input and output. First, from hardware standpoint, do you have any
>> measure about the delay of ADC->CPU->Interrupt call -> Processing ->
>> Output interrupt -> DAC? I guess the whole path will cost you at least
>> a few milliseconds. It means that even your DSP does nothing, an input
>> point will travel a few milliseconds to get sent out. Then you are
>> using a 200 tap FIR. The delay equals another 100 samples points.
>>
>> With such a delay, any control in time domain, with the bandwidth that
>> you asked for, will ends up instable. In the other words, the device
>> can't control anything at such bandwidth.
>>
>> It might be a good idea if you go back to your supervisor, if the task
>> was assigned by him, and discuss the basics of control theory with
>> him.
>
>Better yet, suggest that the supervisor read Wescott's book. :-)
>
>Jerry
>--
>Engineering is the art of making what you want from things you can get.
>ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï ¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿ ½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï ¿½ï¿½ï¿½ï¿½ï¿½
>

Hello all,


I think I wasn't clear enough... my problem is not about the frequency..
it's OK... the delay between samples it's OK as well... the algorithm wor
perfect when I use SISD...

I think my problem is about SIMD... I read in the ADSP21161 manual abou
then problem with the shadow register when use SIMD... my signal 300h
don't change the frequency, it's look a double signal...

Somebody know something about shadow register in SIMD... the manual is no
clear for me....

thanks !!!!

regards
Henrique L. Barcellos