FPGA Central

Is it possible to have parallel cycling system? In this a billion
channels could each have a 1 Hz clock. The goal is to gain a clock
rate of 1 GHz by supplying each of those billion channels with a 1 Hz
clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1
GHz = 1 billion channels. This is called "parallel clocking". One big
advantage I see with this is less heat generated with the same clock
speed.

NOTE: *Hz* is different from *bits* and thus they are not to be
confused with each other.

"Curious" <[email protected]> wrote in message
news:[email protected] om...
> Is it possible to have parallel cycling system? In this a billion
> channels could each have a 1 Hz clock. The goal is to gain a clock
> rate of 1 GHz by supplying each of those billion channels with a 1 Hz
> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1
> GHz = 1 billion channels. This is called "parallel clocking". One big
> advantage I see with this is less heat generated with the same clock
> speed.
>

Sure. But there could be any number of practical problems including real
estate for a billion channels. Also, one must ask why you'd want to have 1
billion clock phases? What would be the purpose? How would you tell them
apart? Would you need to? etc. etc.....

I really don't think it makes sense to talk about it. I've been proven to
be misguided on any number of occasions....

What are you trying to accomnplish exactly?

Fred

On Sat, 10 Jul 2004 17:39:09 -0700, "Fred Marshall"
<fmarshallx@remove_the_x.acm.org> wrote:

>
>"Curious" <[email protected]> wrote in message
>news:[email protected] com...
>> Is it possible to have parallel cycling system?

Yes.

>> In this a billion
>> channels could each have a 1 Hz clock. The goal is to gain a clock
>> rate of 1 GHz by supplying each of those billion channels with a 1 Hz
>> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1
>> GHz = 1 billion channels. This is called "parallel clocking". One big
>> advantage I see with this is less heat generated with the same clock
>> speed.

The heat generated (in modern CMOS logic) is proportional to the
clock rate, but down at 1 Hz the leakage current may dominate. You
generally get the most computation per energy expended by running a
CPU (or other logic block) at full speed.
Look at it this way - a billion processors each running a 1GHz
(using the assumption that one operation is done in one clock cycle,
but this works for getting the approximate order of magnitude) will do
a total of 10^18 operations per second. That would be enough to get
the attention of quite a few US Government agencies...

>Sure. But there could be any number of practical problems including real
>estate for a billion channels.

Last I heard (which may have been years ago) they are approaching a
billion transistors on the lastest high-end CPU chips, that would be
enough for an inverter for each channel. That doesn't seem useful -
maybe when you can do an FFT on a billion points...

>Also, one must ask why you'd want to have 1
>billion clock phases? What would be the purpose? How would you tell them
>apart? Would you need to? etc. etc.....
>
>I really don't think it makes sense to talk about it. I've been proven to
>be misguided on any number of occasions....

Having a billion phases is a bit over-the-top, but I recall a
description of a core memory for a fast (at the time) computer that
used a phased memory. Core memory generally has an access time of one
microsecond. This memory was set up to each consecutive location was
on a different plane of the memory, so that when reading consecutive
memory locations they arrived at 1/8th of a microsecond intervals. Of
course the total bandwidth on average wasn't 8 times that of regular
memory because all accesses aren't sequential, but it was
substantially faster.

>What are you trying to accomnplish exactly?

It looks like a "theoretical question" to me.

>Fred

Curious wrote:

> Is it possible to have parallel cycling system? In this a billion
> channels could each have a 1 Hz clock. The goal is to gain a clock
> rate of 1 GHz by supplying each of those billion channels with a 1 Hz
> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1
> GHz = 1 billion channels. This is called "parallel clocking". One big
> advantage I see with this is less heat generated with the same clock
> speed.
>
> NOTE: *Hz* is different from *bits* and thus they are not to be
> confused with each other.

It is already done, usually once you have everything running as
screamingly fast as possible and you still need more speed.

One example is the "pipelining" that processors do -- generally you'll
have a pipeline stage that fetches an instruction, one that decodes, one
that computes, one that saves, etc. Generally the pipeline will run at
one instruction per clock tick but it will take more than one clock tick
for each instruction to complete. Also generally, the pipeline will
meet certain instructions that make it "stall", i.e. a conditional
branch where the wrong instruction was fetched. Things are fancy these
days, so processors will often have eight or more pipeline stages, and
will reorder the execution of instructions within the pipeline to make
things faster.

Parallel algorithms generally only work where the problem has some
inherent parallel structure to it, and to really gain the speed
improvement the hardware needs to reflect the algorithm. So you could
make a _really fast_ FFT by having each stage of you algorithm do N/2
butterfly calculations; you'd have N multipliers, N adders, and N W
terms, and it would take log_2(N) steps to do it. You could increase
the throughput by having log_2(N) stages, so you could feed a new FFT
source data at each clock tick.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Ben Bradley <[email protected]> wrote in message news:<[email protected]>. ..
> On Sat, 10 Jul 2004 17:39:09 -0700, "Fred Marshall"
> <fmarshallx@remove_the_x.acm.org> wrote:
>
> >
> >"Curious" <[email protected]> wrote in message
> >news:[email protected] com...
> >> Is it possible to have parallel cycling system?
>
> Yes.
>
> >> In this a billion
> >> channels could each have a 1 Hz clock. The goal is to gain a clock
> >> rate of 1 GHz by supplying each of those billion channels with a 1 Hz
> >> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1
> >> GHz = 1 billion channels. This is called "parallel clocking". One big
> >> advantage I see with this is less heat generated with the same clock
> >> speed.
>
> The heat generated (in modern CMOS logic) is proportional to the
> clock rate, but down at 1 Hz the leakage current may dominate. You
> generally get the most computation per energy expended by running a
> CPU (or other logic block) at full speed.
> Look at it this way - a billion processors each running a 1GHz
> (using the assumption that one operation is done in one clock cycle,
> but this works for getting the approximate order of magnitude) will do
> a total of 10^18 operations per second. That would be enough to get
> the attention of quite a few US Government agencies...
>
> >Sure. But there could be any number of practical problems including real
> >estate for a billion channels.
>
> Last I heard (which may have been years ago) they are approaching a
> billion transistors on the lastest high-end CPU chips, that would be
> enough for an inverter for each channel. That doesn't seem useful -
> maybe when you can do an FFT on a billion points...
>
> >Also, one must ask why you'd want to have 1
> >billion clock phases? What would be the purpose? How would you tell them
> >apart? Would you need to? etc. etc.....
> >
> >I really don't think it makes sense to talk about it. I've been proven to
> >be misguided on any number of occasions....
>
> Having a billion phases is a bit over-the-top, but I recall a
> description of a core memory for a fast (at the time) computer that
> used a phased memory. Core memory generally has an access time of one
> microsecond. This memory was set up to each consecutive location was
> on a different plane of the memory, so that when reading consecutive
> memory locations they arrived at 1/8th of a microsecond intervals. Of
> course the total bandwidth on average wasn't 8 times that of regular
> memory because all accesses aren't sequential, but it was
> substantially faster.

If only all algorithms could be "non-sequentialized" :-)

> >What are you trying to accomnplish exactly?
>
> It looks like a "theoretical question" to me.

Yes. The purpose of this "parallel Hz" is to result in a fast clock
rate but at the same time decrease the strain on the clock. For this,
their are the same number of channels for each Hz. 1 Hz = 1 channel. 1
GHz = 1 billion channels.

Tim Wescott <[email protected]> wrote in message news:<[email protected]>...
> Parallel algorithms generally only work where the problem has some
> inherent parallel structure to it, and to really gain the speed
> improvement the hardware needs to reflect the algorithm.
> So you could
> make a _really fast_ FFT by having each stage of you algorithm do N/2
> butterfly calculations; you'd have N multipliers, N adders, and N W
> terms, and it would take log_2(N) steps to do it.


> You could increase
> the throughput by having log_2(N) stages, so you could feed a new FFT
> source data at each clock tick.

What you're describing is parallel "bits" not parallel "hz". My goal
is to somehow gain a clock rate of n ticks/second by giving n channels
each 1 tick/second.

Ben Bradley <[email protected]> wrote in message news:<[email protected]>. ..

> Look at it this way - a billion processors each running a 1GHz

What I was proposing is a billion channels each containing 1 clock.
Each of these clocks work at 1 Hz frequency. The end result should
somehow be a clock rate of 1 GHz when all channels are being used.
This is different from bits per cycle.

Curious wrote:
...
> Yes. The purpose of this "parallel Hz" is to result in a fast clock
> rate but at the same time decrease the strain on the clock. For this,
> their are the same number of channels for each Hz. 1 Hz = 1 channel. 1
> GHz = 1 billion channels.

What do you mean by "strain on the clock"?

Suppose you want to add two numbers, or send out a serial character.
How would that work?

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

On Sun, 11 Jul 2004 01:35:32 -0400, Ben Bradley
<[email protected]> wrote:

>On Sat, 10 Jul 2004 17:39:09 -0700, "Fred Marshall"
><fmarshallx@remove_the_x.acm.org> wrote:
>
>>
>>"Curious" <[email protected]> wrote in message
>>news:[email protected] .com...
>>> Is it possible to have parallel cycling system?
>
> Yes.
>
>>> In this a billion
>>> channels could each have a 1 Hz clock. The goal is to gain a clock
>>> rate of 1 GHz by supplying each of those billion channels with a 1 Hz
>>> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1
>>> GHz = 1 billion channels. This is called "parallel clocking". One big
>>> advantage I see with this is less heat generated with the same clock
>>> speed.
>
> The heat generated (in modern CMOS logic) is proportional to the
>clock rate, but down at 1 Hz the leakage current may dominate. You
>generally get the most computation per energy expended by running a
>CPU (or other logic block) at full speed.

I think for modern CMOS logic (e.g. 0.1something micron), the leakage
current will dominate even if the clock is well above 1MHz.

Regards,
Allan.

Curious wrote:

> What you're describing is parallel "bits" not parallel "hz". My goal
> is to somehow gain a clock rate of n ticks/second by giving n channels
> each 1 tick/second.

Yes, that is rock solid arithmetic.


Bob
--

"Things should be described as simply as possible, but no
simpler."

A. Einstein

Curious wrote:

> Tim Wescott <[email protected]> wrote in message news:<[email protected]>...
>
>>Parallel algorithms generally only work where the problem has some
>>inherent parallel structure to it, and to really gain the speed
>>improvement the hardware needs to reflect the algorithm.
>>So you could
>>make a _really fast_ FFT by having each stage of you algorithm do N/2
>>butterfly calculations; you'd have N multipliers, N adders, and N W
>>terms, and it would take log_2(N) steps to do it.
>
>
>
>>You could increase
>>the throughput by having log_2(N) stages, so you could feed a new FFT
>>source data at each clock tick.
>
>
> What you're describing is parallel "bits" not parallel "hz". My goal
> is to somehow gain a clock rate of n ticks/second by giving n channels
> each 1 tick/second.

If you split your system up into parallel channels you have parallel
bits, however much the idea hurts.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..

> I think for modern CMOS logic (e.g. 0.1something micron), the leakage
> current will dominate even if the clock is well above 1MHz.

What are the consequences of leakage current?

> Regards,
> Allan.

On 12 Jul 2004 21:12:25 -0700, [email protected] (Curious)
wrote:

>Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>
>> I think for modern CMOS logic (e.g. 0.1something micron), the leakage
>> current will dominate even if the clock is well above 1MHz.
>
>What are the consequences of leakage current?

Wasted power, batteries go flat, chip gets hot, etc.

Regards,
Allan.

Curious wrote:

> Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>
>
>>I think for modern CMOS logic (e.g. 0.1something micron), the leakage
>>current will dominate even if the clock is well above 1MHz.
>
>
> What are the consequences of leakage current?
>
>
>>Regards,
>>Allan.

Heat, battery drain.
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

Then there is "the ridiculous obfuscation by language lagniappe"
I wonder if anyone has considered this aspect here?
I think we been had.

Fred

"Tim Wescott" <[email protected]> wrote in message
news:[email protected]..
> Curious wrote:
>
> > Tim Wescott <[email protected]> wrote in message
news:<[email protected]>...
> >
> >>Parallel algorithms generally only work where the problem has some
> >>inherent parallel structure to it, and to really gain the speed
> >>improvement the hardware needs to reflect the algorithm.
> >>So you could
> >>make a _really fast_ FFT by having each stage of you algorithm do N/2
> >>butterfly calculations; you'd have N multipliers, N adders, and N W
> >>terms, and it would take log_2(N) steps to do it.
> >
> >
> >
> >>You could increase
> >>the throughput by having log_2(N) stages, so you could feed a new FFT
> >>source data at each clock tick.
> >
> >
> > What you're describing is parallel "bits" not parallel "hz". My goal
> > is to somehow gain a clock rate of n ticks/second by giving n channels
> > each 1 tick/second.
>
> If you split your system up into parallel channels you have parallel
> bits, however much the idea hurts.
>
> --
>
> Tim Wescott
> Wescott Design Services
> http://www.wescottdesign.com

Fred Marshall wrote:

> Then there is "the ridiculous obfuscation by language lagniappe"
> I wonder if anyone has considered this aspect here?
> I think we been had.
>
> Fred
>
> "Tim Wescott" <[email protected]> wrote in message
> news:[email protected]..
>
>>Curious wrote:
>>
>>
>>>Tim Wescott <[email protected]> wrote in message
>
> news:<[email protected]>...
>
>>>>Parallel algorithms generally only work where the problem has some
>>>>inherent parallel structure to it, and to really gain the speed
>>>>improvement the hardware needs to reflect the algorithm.
>>>>So you could
>>>>make a _really fast_ FFT by having each stage of you algorithm do N/2
>>>>butterfly calculations; you'd have N multipliers, N adders, and N W
>>>>terms, and it would take log_2(N) steps to do it.
>>>
>>>
>>>
>>>>You could increase
>>>>the throughput by having log_2(N) stages, so you could feed a new FFT
>>>>source data at each clock tick.
>>>
>>>
>>>What you're describing is parallel "bits" not parallel "hz". My goal
>>>is to somehow gain a clock rate of n ticks/second by giving n channels
>>>each 1 tick/second.
>>
>>If you split your system up into parallel channels you have parallel
>>bits, however much the idea hurts.
>>
>>--
>>
>>Tim Wescott
>>Wescott Design Services
>>http://www.wescottdesign.com
>
>
>
Well, he had to make five posts to get 10 replies; a 2:1 ratio doesn't
indicate a very good one, does it?

Or, he could be serious.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

"Tim Wescott" <[email protected]> wrote in message
news:[email protected]..
> Well, he had to make five posts to get 10 replies; a 2:1 ratio doesn't
> indicate a very good one, does it?
>
> Or, he could be serious.

Tim,

I dunno. 10 serious replies .....

Yes - of course. But one does have to wonder, doesn't one?

Fred

Fred Marshall wrote:

> "Tim Wescott" <[email protected]> wrote in message
> news:[email protected]..
>
>>Well, he had to make five posts to get 10 replies; a 2:1 ratio doesn't
>>indicate a very good one, does it?
>>
>>Or, he could be serious.
>
>
> Tim,
>
> I dunno. 10 serious replies .....
>
> Yes - of course. But one does have to wonder, doesn't one?
>
> Fred

He knows enough to imagine something, but not enough to actually make
anything. Without what I call self-critical thinking -- searching one's
own ideas for counterexamples and contradictions before putting them
forward -- one usually creates the sort of parody of reality that we
regularly get from Curious. He has a panel of experts to screen his
ideas, and it seems that he doesn't try do do that himself at all. I
occasionally try to guide him by asking what he thinks the implications
of his schemes might be, but he doesn't try to answer.

I've concluded that he's not worth bothering with. He asks us to help
him with self-assigned homework, but he doesn't even try to do it
himself.

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
> On 12 Jul 2004 21:12:25 -0700, [email protected] (Curious)
> wrote:
>
> >Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
> >
> >> I think for modern CMOS logic (e.g. 0.1something micron), the leakage
> >> current will dominate even if the clock is well above 1MHz.
> >
> >What are the consequences of leakage current?
>
> Wasted power, batteries go flat, chip gets hot, etc.

This would be a problem only in electronics. When photonics takes over
will this "parallel Hz" be practical?

Photonics replaces the electric parts in electronics with UV 400 nm
digital lasers.

> Regards,
> Allan.

On 12 Aug 2004 20:38:07 -0700, [email protected] (Curious)
wrote:

>Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>> On 12 Jul 2004 21:12:25 -0700, [email protected] (Curious)
>> wrote:
>>
>> >Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>> >
>> >> I think for modern CMOS logic (e.g. 0.1something micron), the leakage
>> >> current will dominate even if the clock is well above 1MHz.
>> >
>> >What are the consequences of leakage current?
>>
>> Wasted power, batteries go flat, chip gets hot, etc.
>
>This would be a problem only in electronics. When photonics takes over
>will this "parallel Hz" be practical?

Even less so.

>Photonics replaces the electric parts in electronics with UV 400 nm
>digital lasers.

Surely this answers your own question.

Have you ever driven a laser? They require lots of power. An
electronic gate (in the steady state) uses a tiny amount of power due
to leakage currents.

Photonics is used in applications where there is a small amount of
logic toggling rather quickly. This is the opposite of "parallel Hz".

Regards,
Allan.

Curious wrote:

> Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>
>>On 12 Jul 2004 21:12:25 -0700, [email protected] (Curious)
>>wrote:
>>
>>
>>>Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>>>
>>>
>>>>I think for modern CMOS logic (e.g. 0.1something micron), the leakage
>>>>current will dominate even if the clock is well above 1MHz.
>>>
>>>What are the consequences of leakage current?
>>
>>Wasted power, batteries go flat, chip gets hot, etc.
>
>
> This would be a problem only in electronics. When photonics takes over
> will this "parallel Hz" be practical?
>
> Photonics replaces the electric parts in electronics with UV 400 nm
> digital lasers.

Horsefeathers! Methinks you need detectors for the light, too. How many
picowatts are needed to power (a) a laser (b) a sensor (c) a CMOS gate?
Big words don't necessarily imply big ideas.

Jerry
--
.... the worst possible design that just meets the specification - almost
a definition of practical engineering. .. Chris Bore
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
> On 12 Aug 2004 20:38:07 -0700, [email protected] (Curious)
> wrote:
>
> >Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
> >> On 12 Jul 2004 21:12:25 -0700, [email protected] (Curious)
> >> wrote:
> >>
> >> >Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
> >> >
> >> >> I think for modern CMOS logic (e.g. 0.1something micron), the leakage
> >> >> current will dominate even if the clock is well above 1MHz.
> >> >
> >> >What are the consequences of leakage current?
> >>
> >> Wasted power, batteries go flat, chip gets hot, etc.
> >
> >This would be a problem only in electronics. When photonics takes over
> >will this "parallel Hz" be practical?
>
> Even less so.
>
> >Photonics replaces the electric parts in electronics with UV 400 nm
> >digital lasers.
>
> Surely this answers your own question.
>
> Have you ever driven a laser? They require lots of power.

Then why not use large amounts of low-power lasers?

> An
> electronic gate (in the steady state) uses a tiny amount of power due
> to leakage currents.
>
> Photonics is used in applications where there is a small amount of
> logic toggling rather quickly.

What about small amt of logic toggling rather slowly. Photonic
"transistors" -- in my design -- would be 1-bit in resolution and 1 Hz
in clock rate. 1-bit per cycle. 1 sample per bit.

> This is the opposite of "parallel Hz".

No this is different but not opposite.

The "parallel Hz" has channels which are only 1 Hz. You would get 1 Hz
per channel. Lets say you have a billion of these channels. This would
add up to a clock rate of 1 GHz. Each channel is also limited to only
1-bit of resolution. Add up a billion of these channels and you'd get
1 gigabit. In addition, my design allows only 1-bit per cycle and 1
sample per bit.

A truly parallel high-tech system for electronics. For photonics, even
better. Photonics uses 400 nm lasers in place of electricity. The
photonic devices wouldn't even require electricity. They could -- in
theory -- get their energy from genetically-engineered microbes.


> Regards,
> Allan.

On 14 Aug 2004 11:00:34 -0700, [email protected] (Curious)
wrote:

>Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>> On 12 Aug 2004 20:38:07 -0700, [email protected] (Curious)
>> wrote:
>> >This would be a problem only in electronics. When photonics takes over
>> >will this "parallel Hz" be practical?
>>
>> Even less so.
>>
>> >Photonics replaces the electric parts in electronics with UV 400 nm
>> >digital lasers.
>>
>> Surely this answers your own question.
>>
>> Have you ever driven a laser? They require lots of power.
>
>Then why not use large amounts of low-power lasers?

Lasers require a population inversion in whatever material they use.
I believe that uses a lot of power (when compared to the light
output).

I'm not a laser expert so I'll stop there.

Regards,
Allan.

Allan Herriman wrote:

> On 14 Aug 2004 11:00:34 -0700, [email protected] (Curious)
> wrote:
>
>
>>Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
>>
>>>On 12 Aug 2004 20:38:07 -0700, [email protected] (Curious)
>>>wrote:
>>>
>>>>This would be a problem only in electronics. When photonics takes over
>>>>will this "parallel Hz" be practical?
>>>
>>>Even less so.
>>>
>>>
>>>>Photonics replaces the electric parts in electronics with UV 400 nm
>>>>digital lasers.
>>>
>>>Surely this answers your own question.
>>>
>>>Have you ever driven a laser? They require lots of power.
>>
>>Then why not use large amounts of low-power lasers?
>
>
> Lasers require a population inversion in whatever material they use.
> I believe that uses a lot of power (when compared to the light
> output).
>
> I'm not a laser expert so I'll stop there.
>
> Regards,
> Allan.

Power is no problem. You can catch the laser output on a photo cell and
drive the next laser with its output. If the efficiency is high enough,
you only need a battery to start the process, like in a car. :-)

Jerry
--
Where are we going? Why are we in this hand basket?
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

yes

"Curious" <[email protected]> wrote in message
news:34a4f456.0407101311.59dc261d[email protected] om...
> Is it possible to have parallel cycling system? In this a billion
> channels could each have a 1 Hz clock. The goal is to gain a clock
> rate of 1 GHz by supplying each of those billion channels with a 1 Hz
> clock. Each cycle per second has its own channel. 1 Hz = 1 channel. 1
> GHz = 1 billion channels. This is called "parallel clocking". One big
> advantage I see with this is less heat generated with the same clock
> speed.
>
> NOTE: *Hz* is different from *bits* and thus they are not to be
> confused with each other.