FPGA Central

Announcing a Seminar on A New Approach - An FPGA and PCB System
Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10

To register just RSVP http://events.linkedin.com/New-Appro...ent/pub/179766

Agenda

8:00 am Registration / Breakfast
8:30 am Welcome
8:45 am Component & Design Data Management
9:45 am FPGA Design & Instant Prototyping
10:45 am Break
11:00 am ECAD/MCAD with 3D PCB Layout
11:45 am Customer Success with Altium Designer
Noon NanoBoard 3000 Give Away

Session Descriptions

#1 Component and Design Management
Learn how to easily leverage and incorporate supplier component data
into your library. See how to easily version control your designs and
manage ECO’s. Customize your BOM’s and generate release documentation
with the push of a button.

#2 FPGA Design & Instant Prototyping
Learn how to design complex FPGA's with an embedded processor utlizing
block based IP and quickly debug your design in a NanoBoard with
virtual instrumentation.

#3 ECAD/MCAD with 3D PCB Layout
Learn how a 3D PCB layout environment can utilize STEP models to
create a 3D view of the board that can be merged with mechanical
design. Easily verify electrical/ mechanical fit clearances.

For Questions/ Queries Contact:

DACER Solutions, Inc.
Your Silicon Valley Altium Rep
408-712-0500 or 408-202-3416
[email protected]

To register just RSVP http://events.linkedin.com/New-Appro...ent/pub/179766
or
visit http://www.fpgacentral.com/fpga-even...-hotel-5101-gr

On Dec 3, 3:01*pm, Vikram <vkr...@gmail.com> wrote:
> Announcing a Seminar on A New Approach - An FPGA and PCB System
> Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10
>
> #2 FPGA Design & Instant Prototyping
> Learn how to design complex FPGA's with an embedded processor utlizing
> block based IP and quickly debug your design in a NanoBoard with
> virtual instrumentation.

FPGA design using a PCB layout tool is a recipe for disaster.

-a

On Dec 4, 2:09*am, Andy Peters <goo...@latke.net> wrote:
> On Dec 3, 3:01*pm, Vikram <vkr...@gmail.com> wrote:
>
> > Announcing a Seminar on A New Approach - An FPGA and PCB System
> > Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10
>
> > #2 FPGA Design & Instant Prototyping
> > Learn how to design complex FPGA's with an embedded processor utlizing
> > block based IP and quickly debug your design in a NanoBoard with
> > virtual instrumentation.
>
> FPGA design using a PCB layout tool is a recipe for disaster.
>
> -a

Altium Designer is NOT a PCB layotool.

Antti

> FPGA design using a PCB layout tool is a recipe for disaster.

Indeed, I think they're wasting their time down this path.

What is good is the ability to pin/netlist swap when routing and pass
that back to the FPGA constraints. They should concentrate on this and making it
as flexible as possible but forget the FPGA development side of things.


Nial.

On Dec 3, 10:36*pm, Antti <antti.luk...@googlemail.com> wrote:
> On Dec 4, 2:09*am, Andy Peters <goo...@latke.net> wrote:
>
> > On Dec 3, 3:01*pm, Vikram <vkr...@gmail.com> wrote:
>
> > > Announcing a Seminar on A New Approach - An FPGA and PCB System
> > > Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10
>
> > > #2 FPGA Design & Instant Prototyping
> > > Learn how to design complex FPGA's with an embedded processor utlizing
> > > block based IP and quickly debug your design in a NanoBoard with
> > > virtual instrumentation.
>
> > FPGA design using a PCB layout tool is a recipe for disaster.
>
> > -a
>
> Altium Designer is NOT a PCB layotool.

Oh, then how is it possible that I'm doing a board-level schematic in
it right now, which will then be handed off to my layout guy so he can
do that task, also in AD?

-a

Andy Peters wrote:
> On Dec 3, 10:36 pm, Antti <antti.luk...@googlemail.com> wrote:
>> On Dec 4, 2:09 am, Andy Peters <goo...@latke.net> wrote:
>>
>>> On Dec 3, 3:01 pm, Vikram <vkr...@gmail.com> wrote:
>>>> Announcing a Seminar on A New Approach - An FPGA and PCB System
>>>> Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10
>>>> #2 FPGA Design & Instant Prototyping
>>>> Learn how to design complex FPGA's with an embedded processor utlizing
>>>> block based IP and quickly debug your design in a NanoBoard with
>>>> virtual instrumentation.
>>> FPGA design using a PCB layout tool is a recipe for disaster.
>>> -a
>> Altium Designer is NOT a PCB layotool.
>
> Oh, then how is it possible that I'm doing a board-level schematic in
> it right now, which will then be handed off to my layout guy so he can
> do that task, also in AD?
>
> -a

Perhaps Antti meant to say "Altium Designer is not *just* a PCB layout
tool".

It is also a tool for FPGA design (though I haven't tried that aspect of
it myself). Whether or not you think it is a /good/ for FPGA design is
another matter, of course.

Andy Peters <[email protected]> wrote:

>On Dec 3, 10:36=A0pm, Antti <antti.luk...@googlemail.com> wrote:
>> On Dec 4, 2:09=A0am, Andy Peters <goo...@latke.net> wrote:
>>
>> > On Dec 3, 3:01=A0pm, Vikram <vkr...@gmail.com> wrote:
>>
>> > > Announcing a Seminar on A New Approach - An FPGA and PCB System
>> > > Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10
>>
>> > > #2 FPGA Design & Instant Prototyping
>> > > Learn how to design complex FPGA's with an embedded processor utlizin=
>g
>> > > block based IP and quickly debug your design in a NanoBoard with
>> > > virtual instrumentation.
>>
>> > FPGA design using a PCB layout tool is a recipe for disaster.
>>
>> > -a
>>
>> Altium Designer is NOT a PCB layotool.
>
>Oh, then how is it possible that I'm doing a board-level schematic in
>it right now, which will then be handed off to my layout guy so he can
>do that task, also in AD?

Antti should have typed: Altium Designer is NOT *JUST* a PCB layotool.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

On Dec 4, 6:39*am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk > wrote:
> > FPGA design using a PCB layout tool is a recipe for disaster.
>
> Indeed, I think they're wasting their time down this path.
>
> What is good is the ability to pin/netlist swap when routing and pass
> that back to the FPGA constraints. They should concentrate on this and making it
> as flexible as possible but forget the FPGA development side of things.
>
> Nial.

Is the tool FPGA pin type aware? I have found some layout people
don't like to swap pins on FPGAs because it can be very complex due to
the many constraints on pin capability. If the tool is aware of these
limitations, it could help with intelligent swapping.

Rick