FPGA Central

Hye,

I ve been using McBSP bus for communication bewteen several DSP.
One is master and provides the clock for Transmission adn reception to th
other boards.
For the reception, I used interruption generation when XRDY is dectected.
For the transmission i don t use interruption.

All the DSP are in reception status .
The master address the 1st DSP , and wiat ofr the answer (Transmissio
lineis in high impedance).
Then the 2nd then the 3rd....

Each time a DSP is answering, it provides its own frame syncrhonisatio
(FSX).
So when the master receives, it receives the FSX from the slave DSp.


So what i noticed is that when there is a jitter on reception of FS
(received by the Master), the word is missed (no interruption i
provided).
This jitter can be provided by the DSP activities (the sender of th
frame).
The datasheet indicates that it should no be a problem.

Is someone had the same pb?

I haven't used the 2812 McBSP myself but a colleague of mine had a lot
of problems interfacing it to a 2 channel ADC. It's like the McBSP
sometimes seems to loose synchronisation while receiving data.