FPGA Central

I have to program 2 McBSP's (on a 6701)- one as an output and
one as an input - both have to support the same
synchronous protocol: a 1 MHz clock with a 2 KHz frame
sync and a 208 bit data packet. The data starts on the
falling edge of the frame sync. I have read everything I
can find on the TI web site, but I still don't
have a clue what values to put where to generate and
receive the protocol I need to support. All of the
examples put values into the McBSP configuration
registers (either with macros or explicitly), but
none of them explain what the values or the registers
mean. Is there a doc that has the info I need or
any examples out there?

Thanks!
-larry