FPGA Central

QUestion:

Hi all,

Suppose my input data follows Gaussian distribution with mean u and
variance
sigma^2.

If I want to design 6-bit ADC... what should be the optimal step size
for
this ADC?

Thanks a lot

-L

My idea:

When we talk about Analog to Digital conversion we gotta be talking
about signals converted into data. Gaussian distribution gives
information about data or events but not signals.

When we think about which sampling step we shall use, we gotta look to
our signal and analyle which frequency band from our signal has our
information. To sample this information you will need the double
frequency from your frequency band then. More will be better because
just the double will give you problems. But much more won´t give you
any benefecit. Along that you need to include an anti-aliasing filter
between the sampler and your signal orelse you won´t have the
information you want but a distorced sampled signal.

The number of bits also depends on your precision requirement. That
would be very specific I guess.

What I would add about the sample step size that I wonder that is
important is: -If you make your step size too small your frequency of
interest will be too small part from the (-pi/2 until pi/2) continuous
frequency band from your sampled signal, and therefore your filter
development will require a higher order filter. (I´m not so sure about
this but it´s a quick shot)

These are my ideas...

Raul Fajardo