FPGA Central

Hi,
I am implementing the timing recovery model, using Gardner timing erro
detector and the inerpolator. I have implemented interpolator for th
timing recovery in C program in the following manner
- I use two sample per symbol as an input to the interpolator
- I get the offset from the TED at which I calculate the sample valu
using the interpolator.
The output of the interpolator is fed to the TED which would be based o
Gardner algorithm
I have following query
- Would the input data samples to the interpolator be RRC filterd or i
can be directly fed from ADC which samples at twice the symbol rate.
-The Interpolator I have implemented does not upsamples or downsample
rather it just find the sample value at the offset time given by TED. I
this fine..??
- Another doubt I have is that does Gardnee TED works on two symbols whic
are opposite in phase
(I mean they have undergone phase transition). Should the interpolator a
the end of timing recovery sample at the peak value and a zero valuue fo
each symbol

I want to understand how the TED output which is an error value i
translated to offset value that needs to be fed to the interpolator(I kno
its by loop filter but how it works)
Thanks
Regards
Rajenish



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