FPGA Central

Hello,
I am doing simulation studies for frequency and time domain
equalization. From the complexit point of view I completely agreed to
the fact that frequency domain is better in the number of
multiplications/additions. Regarding the performance (BER ) point of
view I can see there is a large 3-4 dB gap between time and domain
equalization.i.e. time domain equalizer is performing better. I am
not sure this result makes sense. Can anyone please clarify this.
My simulation parameters are as follows:
For time domain equalization I am using 31 tap MMSE filter

For requency domain equalization I am using 128 point DFT.

My channel impulse response is modeled as tapped delay line with 3 -
tap Rayleigh channel with delay profile equal to that of Proakis
channel B.

Best Regards,
-SaiRamesh.

On Oct 4, 10:26 am, "sairam...@gmail.com" <nammisairam...@gmail.com>
wrote:
> Hello,
> I am doing simulation studies for frequency and time domain
> equalization. From the complexit point of view I completely agreed to
> the fact that frequency domain is better in the number of
> multiplications/additions. Regarding the performance (BER ) point of
> view I can see there is a large 3-4 dB gap between time and domain
> equalization.i.e. time domain equalizer is performing better. I am
> not sure this result makes sense. Can anyone please clarify this.
> My simulation parameters are as follows:
> For time domain equalization I am using 31 tap MMSE filter
>
> For requency domain equalization I am using 128 point DFT.
>
> My channel impulse response is modeled as tapped delay line with 3 -
> tap Rayleigh channel with delay profile equal to that of Proakis
> channel B.
>
> Best Regards,
> -SaiRamesh.

Did you use a cyclic prefix that is long enough to contain sufficient
channel energy spread?

Julius

Hi,
I am capturing that effect by just using circular convolution
instead of linear convolution and sending the blocks (packets)
independent from each other.

Best Regards,
-SaiRamesh.