FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > DSP

DSP comp.dsp newsgroup, mailing list

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-05-2009, 01:28 PM
vijaym.patel
Guest
 
Posts: n/a
Default DSP side interrupt

Hi,


I am developing a application on DSP side to communication over PCI bu
between my HOST PC(Windows XP) and DM648 EVM.

I use the following peace of code to generate the interrupt to host fro
DSP.

status = readConfigData(pciHandle, PAL_SYSPCI_STATUS_SET,
&interruptStatus);

interruptStatus = interruptStatus | 0x08000000;

/* Set bit in status set register */
status = writeConfigData(pciHandle, PAL_SYSPCI_STATUS_SET,
interruptStatus);

/* Set bit in DSP to Host interrupt register */
status = writeConfigData(pciHandle, PAL_SYSPCI_HOST_INT_ENABLE_SET,
0x08000000);

Now after execution of this code i get interrupt on host side as well a
DSP side.

Is anyone know about this?

Thanking you in anticipation,
Vijay Patel



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Why PCI9054 fails to assert pci interrupt when local interrupt input is pulled down? Any advice? Thanks Leon FPGA 2 08-05-2008 08:35 PM
what is the difference between system side XAUI and line side XAUI? [email protected] FPGA 0 12-29-2007 08:11 AM
out ports on the right side John Smith VHDL 11 10-02-2007 08:48 PM
Data-side BRAM xenix FPGA 0 09-18-2007 02:37 PM
Why Side Lobes appear in magnitude response? Sandeep Chikkerur DSP 5 10-01-2004 02:19 AM


All times are GMT +1. The time now is 01:26 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved