FPGA Central

Hi,

What is the difference between a

- CYCLE ACCURATE SIMULATOR &
- INSTRUCTION ACCURATE SIMUALTOR.

(e.g. ZSP400, ZSP500 Simulators have both the options)

Which is advantageous ?

Thanking in advance.
~ Sandeep

On Wed, 05 Nov 2003 00:23:43 -0800, Sandeep Chikkerur wrote:

> Hi,
>
> What is the difference between a
>
> - CYCLE ACCURATE SIMULATOR &
> - INSTRUCTION ACCURATE SIMUALTOR.
>
> (e.g. ZSP400, ZSP500 Simulators have both the options)
>
> Which is advantageous ?

The terms don't have a universal definition AFIK, but to guess, I'd say:

A cycle-accurate simulator will both run your program *and* tell you how
many cycles it took to execute, perhaps taking things like the number of
configured wait states for external memory accesses and so-on into account.

An instruction-accurate simulator probably just runs your program as fast
as it can: the computations will be according to the instruction set, but
it won't tell you how long each instruction or your whole program will
take. This simulation might run significantly faster than the
cycle-accurate one, perhaps even using a JIT compiler or interpreter, in
the way of a Java VM.

For some things, particularly real-time code, and for detailed
optimization, you need to know how many cycles something will take. At
other times, you just want to know whether or not your code, running in
batch mode (not real-time), is correct or not.

I've often wanted the latter, but have not seen it offered for a DSP
before. If it's what I'm assuming, then that's quite possibly a useful
advance on the part of LSI/ZSP.

--
Andrew

"Andrew Reilly" <andrew@gurney.reilly.home> a écrit dans le message news:
pan.2003.11.05.09.46.22.150461@gurney.reilly.home...
> On Wed, 05 Nov 2003 00:23:43 -0800, Sandeep Chikkerur wrote:
>
> > Hi,
> >
> > What is the difference between a
> >
> > - CYCLE ACCURATE SIMULATOR &
> > - INSTRUCTION ACCURATE SIMUALTOR.
> >
> > (e.g. ZSP400, ZSP500 Simulators have both the options)
> >
> > Which is advantageous ?
>
> The terms don't have a universal definition AFIK, but to guess, I'd say:

Sorry, but I have to disagree even though your guesses
are OK, those terms are universally used as you described
them even though instruction accurate simulators are often
named Instruction Set Simulator.

There exists a third kind of simulator: pin accurate
simulators. Those can be used in HDL simulators using
whatever foreign language interface they use. They are
often run for comparison with VHDL/Verilog implementation.

> I've often wanted the latter, but have not seen it offered for a DSP
> before.

TI offers both kinds simulators for its C6x line of DSP
or at least used to.


Laurent

Sandeep Chikkerur wrote:

> Hi,
>
> What is the difference between a
>
> - CYCLE ACCURATE SIMULATOR &
> - INSTRUCTION ACCURATE SIMUALTOR.
>
> (e.g. ZSP400, ZSP500 Simulators have both the options)
>
> Which is advantageous ?
>
> Thanking in advance.
> ~ Sandeep

Why do you suppose that they offer both? It depends on what you want to
do. Do you want a fast simulation, or do you want to know how many clocks
the actual processor will need, including pipeline faults? Do you always
want the same thing?

Jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

Andrew Reilly <andrew@gurney.reilly.home> wrote in message news:<pan.2003.11.05.09.46.22.150461@gurney.reilly .home>...
> On Wed, 05 Nov 2003 00:23:43 -0800, Sandeep Chikkerur wrote:
>
> > Hi,
> >
> > What is the difference between a
> >
> > - CYCLE ACCURATE SIMULATOR &
> > - INSTRUCTION ACCURATE SIMUALTOR.
> >
> > (e.g. ZSP400, ZSP500 Simulators have both the options)
> >
> > Which is advantageous ?
>
> The terms don't have a universal definition AFIK, but to guess, I'd say:
>
> A cycle-accurate simulator will both run your program *and* tell you how
> many cycles it took to execute, perhaps taking things like the number of
> configured wait states for external memory accesses and so-on into account.
>
> An instruction-accurate simulator probably just runs your program as fast
> as it can: the computations will be according to the instruction set, but
> it won't tell you how long each instruction or your whole program will
> take. This simulation might run significantly faster than the
> cycle-accurate one, perhaps even using a JIT compiler or interpreter, in
> the way of a Java VM.
>
> For some things, particularly real-time code, and for detailed
> optimization, you need to know how many cycles something will take. At
> other times, you just want to know whether or not your code, running in
> batch mode (not real-time), is correct or not.
>
> I've often wanted the latter, but have not seen it offered for a DSP
> before. If it's what I'm assuming, then that's quite possibly a useful
> advance on the part of LSI/ZSP.
High end processor often talks about multi stage
pipelining,VLIW,CLIW,zero loop overhead etc where it is often seen
several simple instructions to execute in single cycle on average.At
the same time one complex instruction like division can take several
cycles. If a requirement is given to design a simulator for these
processor what is the designer's choice? I am familiar with terms like
"MIPS" - Is the second option a better candidate?
Santosh