FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > DSP

DSP comp.dsp newsgroup, mailing list

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-29-2004, 08:54 PM
gooch
Guest
 
Posts: n/a
Default BCH code help

Anyone here have any experience with BCH error correction coding? I
have a project that requires a (252,128) BCH encoding/decoding
capability and am having trouble finding any usefull information on
the subject that is not designed for someone with a Phd in math. Any
pointers, code samples (prefereably for a shorter codeword so I could
actually trace it to see what is going on)or references would be
greatly appreciated. I do have the genereator polynomial and the spec
states I the code is a truncated (255,131) code (I am not really sure
what that means.

I consider myself a fairly smart individual but having no previous
experience with this I am having a hard time with the resources I have
been able to locate.

Thanks
Reply With Quote
  #2 (permalink)  
Old 04-29-2004, 10:03 PM
Dilip V. Sarwate
Guest
 
Posts: n/a
Default Re: BCH code help


"gooch" <[email protected]> asked in
news:[email protected] om...
> Anyone here have any experience with BCH error correction coding?


Try typing in "Coding Cookbook" in Google.


Reply With Quote
  #3 (permalink)  
Old 04-30-2004, 12:19 AM
Kevin Neilson
Guest
 
Posts: n/a
Default Re: BCH code help

"gooch" <[email protected]> wrote in message
news:[email protected] om...
> Anyone here have any experience with BCH error correction coding? I
> have a project that requires a (252,128) BCH encoding/decoding
> capability and am having trouble finding any usefull information on
> the subject that is not designed for someone with a Phd in math. Any
> pointers, code samples (prefereably for a shorter codeword so I could
> actually trace it to see what is going on)or references would be
> greatly appreciated. I do have the genereator polynomial and the spec
> states I the code is a truncated (255,131) code (I am not really sure
> what that means.
>
> I consider myself a fairly smart individual but having no previous
> experience with this I am having a hard time with the resources I have
> been able to locate.
>
> Thanks


Even if you're smart, I think this stuff is really hard to understand.
Peter Sweeney's book is basic, but it does go through some examples with
small codewords so you can actualy work it out by hand. There are some good
links on the follwing site ( http://www.eccpage.com/ ), including Andrew
Lin's GF calculator which will help you work through problems.
-Kevin



Reply With Quote
  #4 (permalink)  
Old 04-30-2004, 10:05 AM
rider
Guest
 
Posts: n/a
Default Re: BCH code help

[email protected] (gooch) wrote in message news:<[email protected] com>...
> Anyone here have any experience with BCH error correction coding? I
> have a project that requires a (252,128) BCH encoding/decoding
> capability and am having trouble finding any usefull information on
> the subject that is not designed for someone with a Phd in math. Any
> pointers, code samples (prefereably for a shorter codeword so I could
> actually trace it to see what is going on)or references would be
> greatly appreciated. I do have the genereator polynomial and the spec
> states I the code is a truncated (255,131) code (I am not really sure
> what that means.
>
> I consider myself a fairly smart individual but having no previous
> experience with this I am having a hard time with the resources I have
> been able to locate.
>
> Thanks


Hi!

When i worked on RS codes some 3 years back, i was also helpless like
you. I was implementing the RS(15,9) code over
GF(2^4). What you are trying to achive is actually a "shortened" code,
i.e. higer order symbols assumed zeros. You should first try to
understand the full-lenght codes like RS(255,223) or RS(15,9). I dont
claim it to be very good, but i wrote a paper on implementation of RS
codes in FPGA for the EDN magazine. I tried to keep mathematics away,
as much as i can. If you want, you might take a look at:

http://www.tmssales.com/Application_...eedsolomon.pdf

(I am Saqib ) ...

Regards
Rider
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Help with Verilog code flow + Code posted. dash82 Verilog 3 11-30-2007 11:13 PM
generating VHDL code from Matlab code for DSP - wavelet image compression EEngineer FPGA 8 02-13-2007 04:22 PM
Looking for 64 bit IEEE802.3 Verilog code or tips for code Vik FPGA 2 12-28-2005 08:53 PM
Verilog Netlest Reader Code, ATPG Code Robert Posey Verilog 0 11-20-2003 12:41 AM
Re: Who will give me some assembly code or some addresses to get such code ? Jaime Andres Aranguren Cardona DSP 2 08-16-2003 03:46 PM


All times are GMT +1. The time now is 12:47 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved