FPGA Central

Data converters (ADCs and DACs) ultimately limit the performance of today'
communication systems. New concepts for high-speed, high-resolution, an
power-aware converters are therefore required, which also lead to a
increased demand for high-speed and high-resolution sampling systems i
the measurement industry. Present converter technologies operate on thei
limits, since the downscaling of IC technologies to deep submicro
technologies makes their design increasingly difficult. Fortunately
downscaling of IC technologies allows for using additional chip area fo
digital signal processing algorithms with hardly any additional costs
Therefore, one can use more elaborate signal processing algorithms t
improve the conversion quality, to realize new converter architectures an
technologies, or to relax the requirements on the analog design. Pipeline
ADCs constitute just one example of converter technology where signa
processing algorithms are already extensively used. However
time-interleaved converters and their generalizations, including hybri
filter bank-based converters and parallel sigma-delta-based converters
are the next candidates for digitally enhanced converter technologies
where advanced signal processing is essential. Accurate models constitut
one foundation of digital corrected data converters. Generating an
verifying such models is a complex and time-consuming process that demand
high-performance instrumentation in conjunction with sophisticated softwar
defined measurements.

The aim of this special issue is to bring forward recent developments o
signal processing methods for data converters. It includes design
analysis, and implementation of enhancement algorithms as well as signa
processing aspects of new converter topologies and sampling strategies
Further, it includes design, analysis, and implementation of softwar
defined measurements for characterization and modeling of dat
converters.

Topics of interest include (but are not limited to):

* Analysis, design, and implementation of digital algorithms for dat
converters
* Analysis and modeling of novel converter topologies and their signal
processing aspects
* Digital calibration of data converters
* Error identification and correction in time-interleaved ADCs and
their generalizations
* Signal processing for application-specific data converter
(communication systems, measurement systems, etc.)
* New sampling strategies
* Sampling theory for data converters
* Signal processing algorithms for data converter testing
* Influence of technology scaling on data converters and their design
* Behavioral models for converter characterization
* Instrumentation and software defined measurements for converter
characterization

Authors should follow the EURASIP JASP manuscript format described at th
journal site http://www.hindawi.com/journals/asp/. Prospective author
should submit an electronic copy of their complete manuscript through th
EURASIP JASP Manuscript Tracking System at http://www.hindawi.com/mts/
according to the following timetable:

Manuscript Due May 1, 2007
First Round of Reviews September 1, 2007
Publication Date January 1, 2008




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