FPGA Central

I posted a message a couple of months ago on a PLL I am working on,
but I can't continue that thread. The circuit is using a PLL to
generate an output clock which is a integer ratio multiple of the
input clock. The purpose is to pull data out of a FIFO at the same
rate it is going in and to keep a fixed amount of data in the FIFO
while driving the output which is an interleave circuit. So the
output clock needs to be N/(N-1) times the input clock and the PLL
must maintain a zero phase relationship (long term) between the input
clock and the divided down output clock in order to keep amount of
data in the FIFO constant.

The circuit I came up with for this uses an up/down counter as the
phase comparator. The the leading edge of the input clock makes it
count up and the leading edge of the feedback clock makes it count
down. If both occur during a given system clock cycle, the count is
held as it is when there are no leading edges.

From what I have seen, this is considered a bang-bang phase comparator
in the analog world. I guess it works the same in the digital world
too. The filter I am using is an integrator added to a proportional
(each with gain factors) to produce the step size fed to the NCO. The
NCO produces a clock enable on overflow which feeds the interleave
circuit. The interleave circuit returns N-1 out of every N clocks to
pull data out of the FIFO and feedback to the PLL.

I simulated this with gain settings of A=64 for the proportional path
and B=1/128 for the integrator output. I also tried other values and
they are all stable, but some settle faster and others ring more
before settling. I picked the values that seem to give me quick
settling and track an input frequency change well without a lot of
oscillation.

All that said, when I do an analysis of the filter using the z-
transform, I get a pole on the unit circle at 1,0 and a zero very
close to it at 0.999...,0. It would appear that the zero is
stabilizing the pole and frequencies other than very near DC. But a
DC input is stabilized by the overall loop. The question is, how do I
include the rest of the loop in a z-transform analysis? Or is this
not the right way to approach it?

Rick

On May 29, 6:15*pm, rickman <gnu...@gmail.com> wrote:
> I posted a message a couple of months ago on a PLL I am working on,
> but I can't continue that thread. *The circuit is using a PLL to
> generate an output clock which is a integer ratio multiple of the
> input clock. *The purpose is to pull data out of a FIFO at the same
> rate it is going in and to keep a fixed amount of data in the FIFO
> while driving the output which is an interleave circuit. *So the
> output clock needs to be N/(N-1) times the input clock and the PLL
> must maintain a zero phase relationship (long term) between the input
> clock and the divided down output clock in order to keep amount of
> data in the FIFO constant.
>
> The circuit I came up with for this uses an up/down counter as the
> phase comparator. *The the leading edge of the input clock makes it
> count up and the leading edge of the feedback clock makes it count
> down. *If both occur during a given system clock cycle, the count is
> held as it is when there are no leading edges.
>
> From what I have seen, this is considered a bang-bang phase comparator
> in the analog world. *I guess it works the same in the digital world
> too. *The filter I am using is an integrator added to a proportional
> (each with gain factors) to produce the step size fed to the NCO. *The
> NCO produces a clock enable on overflow which feeds the interleave
> circuit. *The interleave circuit returns N-1 out of every N clocks to
> pull data out of the FIFO and feedback to the PLL.
>
> I simulated this with gain settings of A=64 for the proportional path
> and B=1/128 for the integrator output. *I also tried other values and
> they are all stable, but some settle faster and others ring more
> before settling. *I picked the values that seem to give me quick
> settling and track an input frequency change well without a lot of
> oscillation.
>
> All that said, when I do an analysis of the filter using the z-
> transform, I get a pole on the unit circle at 1,0 and a zero very
> close to it at 0.999...,0. *It would appear that the zero is
> stabilizing the pole and frequencies other than very near DC. *But a
> DC input is stabilized by the overall loop. *The question is, how do I
> include the rest of the loop in a z-transform analysis? *Or is this
> not the right way to approach it?
>
> Rick

First clarification...when you say digital PLL, is this all in DSP,
i.e. is it an NCO or a VCO with a real control voltage?

The full loop is analyzed with the KVco the gain of the VCO (or NCO)
and the gain of the phase detector. Since the VCO generates a
frequency and the phase detector detects a phase, the combination
produces a pole at DC or an integrator.

Mark

On May 29, 6:35*pm, makol...@yahoo.com wrote:
> On May 29, 6:15*pm, rickman <gnu...@gmail.com> wrote:
>
>
>
> > I posted a message a couple of months ago on a PLL I am working on,
> > but I can't continue that thread. *The circuit is using a PLL to
> > generate an output clock which is a integer ratio multiple of the
> > input clock. *The purpose is to pull data out of a FIFO at the same
> > rate it is going in and to keep a fixed amount of data in the FIFO
> > while driving the output which is an interleave circuit. *So the
> > output clock needs to be N/(N-1) times the input clock and the PLL
> > must maintain a zero phase relationship (long term) between the input
> > clock and the divided down output clock in order to keep amount of
> > data in the FIFO constant.
>
> > The circuit I came up with for this uses an up/down counter as the
> > phase comparator. *The the leading edge of the input clock makes it
> > count up and the leading edge of the feedback clock makes it count
> > down. *If both occur during a given system clock cycle, the count is
> > held as it is when there are no leading edges.
>
> > From what I have seen, this is considered a bang-bang phase comparator
> > in the analog world. *I guess it works the same in the digital world
> > too. *The filter I am using is an integrator added to a proportional
> > (each with gain factors) to produce the step size fed to the NCO. *The
> > NCO produces a clock enable on overflow which feeds the interleave
> > circuit. *The interleave circuit returns N-1 out of every N clocks to
> > pull data out of the FIFO and feedback to the PLL.
>
> > I simulated this with gain settings of A=64 for the proportional path
> > and B=1/128 for the integrator output. *I also tried other values and
> > they are all stable, but some settle faster and others ring more
> > before settling. *I picked the values that seem to give me quick
> > settling and track an input frequency change well without a lot of
> > oscillation.
>
> > All that said, when I do an analysis of the filter using the z-
> > transform, I get a pole on the unit circle at 1,0 and a zero very
> > close to it at 0.999...,0. *It would appear that the zero is
> > stabilizing the pole and frequencies other than very near DC. *But a
> > DC input is stabilized by the overall loop. *The question is, how do I
> > include the rest of the loop in a z-transform analysis? *Or is this
> > not the right way to approach it?
>
> > Rick
>
> First clarification...when you say digital PLL, is this all in DSP,
> i.e. is it an NCO *or a VCO with a real control voltage?
>
> The full loop is analyzed with the KVco the gain of the VCO (or NCO)
> and the gain of the phase detector. *Since the VCO generates a
> frequency and the phase detector detects a phase, the combination
> produces a pole at DC or an integrator.
>
> Mark

All digital as in an FPGA. No VCO and no NCO, it uses a DCO. I was
mistaken when I used the term NCO.

There is also an integrator in the filter. The filter integrator is
necessary to drive the error output of the phase comparator to zero.

When you say the DCO and phase comparator produce a pole at DC, where
exactly is this DC determined? Are you referring to a DC input as in
0 Hz? I believe if you have a 0 Hz input and your filter does not
include an integrator, the output will be 0 Hz. Am I missing
something?

Rick

On May 29, 6:53*pm, rickman <gnu...@gmail.com> wrote:
> On May 29, 6:35*pm, makol...@yahoo.com wrote:
>
>
>
> > On May 29, 6:15*pm, rickman <gnu...@gmail.com> wrote:
>
> > > I posted a message a couple of months ago on a PLL I am working on,
> > > but I can't continue that thread. *The circuit is using a PLL to
> > > generate an output clock which is a integer ratio multiple of the
> > > input clock. *The purpose is to pull data out of a FIFO at the same
> > > rate it is going in and to keep a fixed amount of data in the FIFO
> > > while driving the output which is an interleave circuit. *So the
> > > output clock needs to be N/(N-1) times the input clock and the PLL
> > > must maintain a zero phase relationship (long term) between the input
> > > clock and the divided down output clock in order to keep amount of
> > > data in the FIFO constant.
>
> > > The circuit I came up with for this uses an up/down counter as the
> > > phase comparator. *The the leading edge of the input clock makes it
> > > count up and the leading edge of the feedback clock makes it count
> > > down. *If both occur during a given system clock cycle, the count is
> > > held as it is when there are no leading edges.
>
> > > From what I have seen, this is considered a bang-bang phase comparator
> > > in the analog world. *I guess it works the same in the digital world
> > > too. *The filter I am using is an integrator added to a proportional
> > > (each with gain factors) to produce the step size fed to the NCO. *The
> > > NCO produces a clock enable on overflow which feeds the interleave
> > > circuit. *The interleave circuit returns N-1 out of every N clocks to
> > > pull data out of the FIFO and feedback to the PLL.
>
> > > I simulated this with gain settings of A=64 for the proportional path
> > > and B=1/128 for the integrator output. *I also tried other valuesand
> > > they are all stable, but some settle faster and others ring more
> > > before settling. *I picked the values that seem to give me quick
> > > settling and track an input frequency change well without a lot of
> > > oscillation.
>
> > > All that said, when I do an analysis of the filter using the z-
> > > transform, I get a pole on the unit circle at 1,0 and a zero very
> > > close to it at 0.999...,0. *It would appear that the zero is
> > > stabilizing the pole and frequencies other than very near DC. *But a
> > > DC input is stabilized by the overall loop. *The question is, how do I
> > > include the rest of the loop in a z-transform analysis? *Or is this
> > > not the right way to approach it?
>
> > > Rick
>
> > First clarification...when you say digital PLL, is this all in DSP,
> > i.e. is it an NCO *or a VCO with a real control voltage?
>
> > The full loop is analyzed with the KVco the gain of the VCO (or NCO)
> > and the gain of the phase detector. *Since the VCO generates a
> > frequency and the phase detector detects a phase, the combination
> > produces a pole at DC or an integrator.
>
> > Mark
>
> All digital as in an FPGA. *No VCO and no NCO, it uses a DCO. *I was
> mistaken when I used the term NCO.

what's the difference between a Numerically-Controlled Oscillator and
a Digitally-Controlled Oscillator?

> There is also an integrator in the filter. *The filter integrator is
> necessary to drive the error output of the phase comparator to zero.

but there is also an inherent integrator in the DCO.

> When you say the DCO and phase comparator produce a pole at DC, where
> exactly is this DC determined? *Are you referring to a DC input as in
> 0 Hz? *I believe if you have a 0 Hz input and your filter does not
> include an integrator, the output will be 0 Hz. *Am I missing
> something?

i am not sure if you're missing this or not, but in case you are,
please lemme spell it out:

1. the output frequency of the DCO is presumed to be proportional to
the input control paramenter.

2. frequency is the derivative of phase w.r.t. time. that means if
you are going to relate *unwrapped* phase to frequency it's like the
frequency parameter goes into an integrator and out comes phase.

3. the phase comparator compares the phase of the output of the DCO to
the input waveform (which we assume is periodic) and gives you a
result which is a number (or a pseudo-"voltage") which is proportional
to that phase difference.

4. that phase difference is fed back through whatever gain and
whatever other LTI system (or it might not all be linear, you might
want to put some hard limiting in there or something else to help you
hunt and lock when the frequencies are widely different). because in
a discrete-time system we cannot have a closed loop with zero delay
(we only know the previous output values to be used in the computation
of the current input, we cannot know the current output for the
current input), then there is necessarily a delay element in that
feedback LTI system *must* have an overall 1/z factor in it.

5. so, even with the simplest proportional controller (no I or D in
the PID), you will necessarily have an integrator (1/(1-1/z)) and
another delay (1/z) in the loop. that cannot be avoided. now, if you
choose to add more stuff than a P in your PID controller, you may, but
your loop gain must have at least a 1/z * 1/(1-1/z) in it.

dunno if any of this is helpful.

r b-j

On Fri, 29 May 2009 15:15:38 -0700, rickman wrote:

> The circuit I came up with for this uses an up/down counter as the phase
> comparator. The the leading edge of the input clock makes it count up
> and the leading edge of the feedback clock makes it count down. If both
> occur during a given system clock cycle, the count is held as it is when
> there are no leading edges.
>
> From what I have seen, this is considered a bang-bang phase comparator
> in the analog world. I guess it works the same in the digital world
> too.

It's *not* bang-bang. Consider the case of frequency lock with a phase
offset: the output of the phase detector will be an integer, but the time
average of the output can sit between two integers. Indeed, it will be
linear and capable of resolving tiny phase differences, more so than an
analog phase detector (which will always have /some/ non-linearity).

It is quite reasonable to consider the average of the output because the
phase detector is always followed by a (lowpass-ish) loop filter and an
integrator (the vco or nco), and the loop bandwidth will usually be
orders of magnitude less than the phase comparison frequency.

Example: the input clock leads the feedback by pi radians. The output
will be a square wave with a 50% duty cycle, giving it an average value
of 1/2.

BTW, I've always put a clipper on the output of the phase detector (which
is actually done by not letting the counter wrap around). The clip level
should be symmetric (e.g. +/- x). When locked, the output will usually
be in the range -1 to +1 anyway, and the clipping helps prevent loop
filter windup during initial acquisition, although it does limit the
frequency slew rate.


> The filter I am using is an integrator added to a proportional
> (each with gain factors) to produce the step size fed to the NCO. The
> NCO produces a clock enable on overflow which feeds the interleave
> circuit. The interleave circuit returns N-1 out of every N clocks to
> pull data out of the FIFO and feedback to the PLL.
>
> I simulated this with gain settings of A=64 for the proportional path
> and B=1/128 for the integrator output. I also tried other values and
> they are all stable, but some settle faster and others ring more before
> settling. I picked the values that seem to give me quick settling and
> track an input frequency change well without a lot of oscillation.

My experience here has been that it can be difficult to achieve good
performance by experiment, even though there are only two independent
variables (the gain and the zero location, which can be transformed into
or from your A and B gains).

My approach has been to decide what performance I want, work out where
the closed loop poles and zero have to be from that, then work out the
various gains. Then test. Assuming I have adequate word widths
everywhere (to avoid accidental clipping), it will test the way I expect
first time.

> All that said, when I do an analysis of the filter using the z-
> transform, I get a pole on the unit circle at 1,0 and a zero very close
> to it at 0.999...,0. It would appear that the zero is stabilizing the
> pole and frequencies other than very near DC. But a DC input is
> stabilized by the overall loop. The question is, how do I include the
> rest of the loop in a z-transform analysis? Or is this not the right
> way to approach it?

If you use the averaging approximation to the phase detector, you might
as well go the whole way and ignore sampling effects altogether and use
the Laplace transform instead of the Z transform. This will give you
accurate results provided that the sampling rate is high enough with
respect to your loop bandwidth.

The loop analysis should take you about as long as it's taken me to write
this news posting. I guess the trick is to work out which parts must be
calculated exactly, and which parts can be handled with a simple (e.g.
linearity or continuous time) approximation. This only comes with
experience, and I suspect you already have that experience.

Other things you might like to consider:
The "error gain". This is the transfer function from the input phase
(jitter) to the error phase (being the difference between the input phase
and the feedback phase). Since the error phase determines FIFO depth,
you can work out whether your FIFO will overflow based on input phase
transients, etc.

Regards,
Allan

On May 29, 10:58 pm, robert bristow-johnson
<r...@audioimagination.com> wrote:
> On May 29, 6:53 pm, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On May 29, 6:35 pm, makol...@yahoo.com wrote:
>
> > > On May 29, 6:15 pm, rickman <gnu...@gmail.com> wrote:
>
> > > > I posted a message a couple of months ago on a PLL I am working on,
> > > > but I can't continue that thread. The circuit is using a PLL to
> > > > generate an output clock which is a integer ratio multiple of the
> > > > input clock. The purpose is to pull data out of a FIFO at the same
> > > > rate it is going in and to keep a fixed amount of data in the FIFO
> > > > while driving the output which is an interleave circuit. So the
> > > > output clock needs to be N/(N-1) times the input clock and the PLL
> > > > must maintain a zero phase relationship (long term) between the input
> > > > clock and the divided down output clock in order to keep amount of
> > > > data in the FIFO constant.
>
> > > > The circuit I came up with for this uses an up/down counter as the
> > > > phase comparator. The the leading edge of the input clock makes it
> > > > count up and the leading edge of the feedback clock makes it count
> > > > down. If both occur during a given system clock cycle, the count is
> > > > held as it is when there are no leading edges.
>
> > > > From what I have seen, this is considered a bang-bang phase comparator
> > > > in the analog world. I guess it works the same in the digital world
> > > > too. The filter I am using is an integrator added to a proportional
> > > > (each with gain factors) to produce the step size fed to the NCO. The
> > > > NCO produces a clock enable on overflow which feeds the interleave
> > > > circuit. The interleave circuit returns N-1 out of every N clocks to
> > > > pull data out of the FIFO and feedback to the PLL.
>
> > > > I simulated this with gain settings of A=64 for the proportional path
> > > > and B=1/128 for the integrator output. I also tried other values and
> > > > they are all stable, but some settle faster and others ring more
> > > > before settling. I picked the values that seem to give me quick
> > > > settling and track an input frequency change well without a lot of
> > > > oscillation.
>
> > > > All that said, when I do an analysis of the filter using the z-
> > > > transform, I get a pole on the unit circle at 1,0 and a zero very
> > > > close to it at 0.999...,0. It would appear that the zero is
> > > > stabilizing the pole and frequencies other than very near DC. But a
> > > > DC input is stabilized by the overall loop. The question is, how do I
> > > > include the rest of the loop in a z-transform analysis? Or is this
> > > > not the right way to approach it?
>
> > > > Rick
>
> > > First clarification...when you say digital PLL, is this all in DSP,
> > > i.e. is it an NCO or a VCO with a real control voltage?
>
> > > The full loop is analyzed with the KVco the gain of the VCO (or NCO)
> > > and the gain of the phase detector. Since the VCO generates a
> > > frequency and the phase detector detects a phase, the combination
> > > produces a pole at DC or an integrator.
>
> > > Mark
>
> > All digital as in an FPGA. No VCO and no NCO, it uses a DCO. I was
> > mistaken when I used the term NCO.
>
> what's the difference between a Numerically-Controlled Oscillator and
> a Digitally-Controlled Oscillator?

I didn't think there was any, but it was explained to me that an NCO
has the lookup table to generate a sine/cosine output while a DCO just
provides either the upper bit to generate a square wave, or the carry
out to generate a one pulse per roll over. I used to use them
interchangeably, but I found this difference documented somewhere on
the web, so it must be true.


> > There is also an integrator in the filter. The filter integrator is
> > necessary to drive the error output of the phase comparator to zero.
>
> but there is also an inherent integrator in the DCO.

Yes, I wasn't trying to say this was different, just to get the
terminology correct. He was asking if it was a hardware VCO or
something else.


> > When you say the DCO and phase comparator produce a pole at DC, where
> > exactly is this DC determined? Are you referring to a DC input as in
> > 0 Hz? I believe if you have a 0 Hz input and your filter does not
> > include an integrator, the output will be 0 Hz. Am I missing
> > something?
>
> i am not sure if you're missing this or not, but in case you are,
> please lemme spell it out:
>
> 1. the output frequency of the DCO is presumed to be proportional to
> the input control paramenter.
>
> 2. frequency is the derivative of phase w.r.t. time. that means if
> you are going to relate *unwrapped* phase to frequency it's like the
> frequency parameter goes into an integrator and out comes phase.
>
> 3. the phase comparator compares the phase of the output of the DCO to
> the input waveform (which we assume is periodic) and gives you a
> result which is a number (or a pseudo-"voltage") which is proportional
> to that phase difference.
>
> 4. that phase difference is fed back through whatever gain and
> whatever other LTI system (or it might not all be linear, you might
> want to put some hard limiting in there or something else to help you
> hunt and lock when the frequencies are widely different). because in
> a discrete-time system we cannot have a closed loop with zero delay
> (we only know the previous output values to be used in the computation
> of the current input, we cannot know the current output for the
> current input), then there is necessarily a delay element in that
> feedback LTI system *must* have an overall 1/z factor in it.
>
> 5. so, even with the simplest proportional controller (no I or D in
> the PID), you will necessarily have an integrator (1/(1-1/z)) and
> another delay (1/z) in the loop. that cannot be avoided. now, if you
> choose to add more stuff than a P in your PID controller, you may, but
> your loop gain must have at least a 1/z * 1/(1-1/z) in it.
>
> dunno if any of this is helpful.
>
> r b-j

Thanks for the info. I am aware of everything you wrote. I just am
having trouble doing the math for it. My "filter" only needs an
integrator which will allow the error signal out of the phase detector
to become zero for any given frequency input. But this is not a
stable configuration. I added a proportional feedback which helps to
stabilize the loop. I can analyze the filter, but I'm not clear on
how to analyze the entire loop.

Rick

On Fri, 29 May 2009 21:57:44 -0700, rickman wrote:

> On May 29, 10:58 pm, robert bristow-johnson <r...@audioimagination.com>
> wrote:
>> On May 29, 6:53 pm, rickman <gnu...@gmail.com> wrote:
>>
>>
>>
>> > On May 29, 6:35 pm, makol...@yahoo.com wrote:
>>
>> > > On May 29, 6:15 pm, rickman <gnu...@gmail.com> wrote:
>>
>> > > > I posted a message a couple of months ago on a PLL I am working
>> > > > on, but I can't continue that thread. The circuit is using a PLL
>> > > > to generate an output clock which is a integer ratio multiple of
>> > > > the input clock. The purpose is to pull data out of a FIFO at
>> > > > the same rate it is going in and to keep a fixed amount of data
>> > > > in the FIFO while driving the output which is an interleave
>> > > > circuit. So the output clock needs to be N/(N-1) times the input
>> > > > clock and the PLL must maintain a zero phase relationship (long
>> > > > term) between the input clock and the divided down output clock
>> > > > in order to keep amount of data in the FIFO constant.
>>
>> > > > The circuit I came up with for this uses an up/down counter as
>> > > > the phase comparator. The the leading edge of the input clock
>> > > > makes it count up and the leading edge of the feedback clock
>> > > > makes it count down. If both occur during a given system clock
>> > > > cycle, the count is held as it is when there are no leading
>> > > > edges.
>>
>> > > > From what I have seen, this is considered a bang-bang phase
>> > > > comparator in the analog world. I guess it works the same in the
>> > > > digital world too. The filter I am using is an integrator added
>> > > > to a proportional (each with gain factors) to produce the step
>> > > > size fed to the NCO. The NCO produces a clock enable on overflow
>> > > > which feeds the interleave circuit. The interleave circuit
>> > > > returns N-1 out of every N clocks to pull data out of the FIFO
>> > > > and feedback to the PLL.
>>
>> > > > I simulated this with gain settings of A=64 for the proportional
>> > > > path and B=1/128 for the integrator output. I also tried other
>> > > > values and they are all stable, but some settle faster and others
>> > > > ring more before settling. I picked the values that seem to give
>> > > > me quick settling and track an input frequency change well
>> > > > without a lot of oscillation.
>>
>> > > > All that said, when I do an analysis of the filter using the z-
>> > > > transform, I get a pole on the unit circle at 1,0 and a zero very
>> > > > close to it at 0.999...,0. It would appear that the zero is
>> > > > stabilizing the pole and frequencies other than very near DC.
>> > > > But a DC input is stabilized by the overall loop. The question
>> > > > is, how do I include the rest of the loop in a z-transform
>> > > > analysis? Or is this not the right way to approach it?
>>
>> > > > Rick
>>
>> > > First clarification...when you say digital PLL, is this all in DSP,
>> > > i.e. is it an NCO or a VCO with a real control voltage?
>>
>> > > The full loop is analyzed with the KVco the gain of the VCO (or
>> > > NCO) and the gain of the phase detector. Since the VCO generates a
>> > > frequency and the phase detector detects a phase, the combination
>> > > produces a pole at DC or an integrator.
>>
>> > > Mark
>>
>> > All digital as in an FPGA. No VCO and no NCO, it uses a DCO. I was
>> > mistaken when I used the term NCO.
>>
>> what's the difference between a Numerically-Controlled Oscillator and a
>> Digitally-Controlled Oscillator?
>
> I didn't think there was any, but it was explained to me that an NCO has
> the lookup table to generate a sine/cosine output while a DCO just
> provides either the upper bit to generate a square wave, or the carry
> out to generate a one pulse per roll over. I used to use them
> interchangeably, but I found this difference documented somewhere on the
> web, so it must be true.
>
>
>> > There is also an integrator in the filter. The filter integrator is
>> > necessary to drive the error output of the phase comparator to zero.
>>
>> but there is also an inherent integrator in the DCO.
>
> Yes, I wasn't trying to say this was different, just to get the
> terminology correct. He was asking if it was a hardware VCO or
> something else.
>
>
>> > When you say the DCO and phase comparator produce a pole at DC, where
>> > exactly is this DC determined? Are you referring to a DC input as in
>> > 0 Hz? I believe if you have a 0 Hz input and your filter does not
>> > include an integrator, the output will be 0 Hz. Am I missing
>> > something?
>>
>> i am not sure if you're missing this or not, but in case you are,
>> please lemme spell it out:
>>
>> 1. the output frequency of the DCO is presumed to be proportional to
>> the input control paramenter.
>>
>> 2. frequency is the derivative of phase w.r.t. time. that means if you
>> are going to relate *unwrapped* phase to frequency it's like the
>> frequency parameter goes into an integrator and out comes phase.
>>
>> 3. the phase comparator compares the phase of the output of the DCO to
>> the input waveform (which we assume is periodic) and gives you a result
>> which is a number (or a pseudo-"voltage") which is proportional to that
>> phase difference.
>>
>> 4. that phase difference is fed back through whatever gain and whatever
>> other LTI system (or it might not all be linear, you might want to put
>> some hard limiting in there or something else to help you hunt and lock
>> when the frequencies are widely different). because in a discrete-time
>> system we cannot have a closed loop with zero delay (we only know the
>> previous output values to be used in the computation of the current
>> input, we cannot know the current output for the current input), then
>> there is necessarily a delay element in that feedback LTI system *must*
>> have an overall 1/z factor in it.
>>
>> 5. so, even with the simplest proportional controller (no I or D in the
>> PID), you will necessarily have an integrator (1/(1-1/z)) and another
>> delay (1/z) in the loop. that cannot be avoided. now, if you choose
>> to add more stuff than a P in your PID controller, you may, but your
>> loop gain must have at least a 1/z * 1/(1-1/z) in it.
>>
>> dunno if any of this is helpful.
>>
>> r b-j
>
> Thanks for the info. I am aware of everything you wrote. I just am
> having trouble doing the math for it. My "filter" only needs an
> integrator which will allow the error signal out of the phase detector
> to become zero for any given frequency input. But this is not a stable
> configuration. I added a proportional feedback which helps to stabilize
> the loop. I can analyze the filter, but I'm not clear on how to analyze
> the entire loop.


Rick, can you clarify something please? Are you having a problem with
the algebra, or are you having a problem with modelling the design?

By "the algebra" I mean turning the transfer functions of the various
parts (loop filter, nco, etc.) into a transfer function of the entire
system.

By "modelling the design", I mean turning your implementation of the
various parts (e.g. adders, counters, accumulators, etc.) into transfer
functions. If you haven't done this before, it may not be immediately
obvious how to work out something like Kv for your NCO or the phase
detector gain.

Thanks,
Allan

On May 30, 5:13 am, Allan Herriman <allanherri...@hotmail.com> wrote:
> On Fri, 29 May 2009 21:57:44 -0700, rickman wrote:
> > On May 29, 10:58 pm, robert bristow-johnson <r...@audioimagination.com>
> > wrote:
> >> On May 29, 6:53 pm, rickman <gnu...@gmail.com> wrote:
>
> >> > On May 29, 6:35 pm, makol...@yahoo.com wrote:
>
> >> > > On May 29, 6:15 pm, rickman <gnu...@gmail.com> wrote:
>
> >> > > > I posted a message a couple of months ago on a PLL I am working
> >> > > > on, but I can't continue that thread. The circuit is using a PLL
> >> > > > to generate an output clock which is a integer ratio multiple of
> >> > > > the input clock. The purpose is to pull data out of a FIFO at
> >> > > > the same rate it is going in and to keep a fixed amount of data
> >> > > > in the FIFO while driving the output which is an interleave
> >> > > > circuit. So the output clock needs to be N/(N-1) times the input
> >> > > > clock and the PLL must maintain a zero phase relationship (long
> >> > > > term) between the input clock and the divided down output clock
> >> > > > in order to keep amount of data in the FIFO constant.
>
> >> > > > The circuit I came up with for this uses an up/down counter as
> >> > > > the phase comparator. The the leading edge of the input clock
> >> > > > makes it count up and the leading edge of the feedback clock
> >> > > > makes it count down. If both occur during a given system clock
> >> > > > cycle, the count is held as it is when there are no leading
> >> > > > edges.
>
> >> > > > From what I have seen, this is considered a bang-bang phase
> >> > > > comparator in the analog world. I guess it works the same in the
> >> > > > digital world too. The filter I am using is an integrator added
> >> > > > to a proportional (each with gain factors) to produce the step
> >> > > > size fed to the NCO. The NCO produces a clock enable on overflow
> >> > > > which feeds the interleave circuit. The interleave circuit
> >> > > > returns N-1 out of every N clocks to pull data out of the FIFO
> >> > > > and feedback to the PLL.
>
> >> > > > I simulated this with gain settings of A=64 for the proportional
> >> > > > path and B=1/128 for the integrator output. I also tried other
> >> > > > values and they are all stable, but some settle faster and others
> >> > > > ring more before settling. I picked the values that seem to give
> >> > > > me quick settling and track an input frequency change well
> >> > > > without a lot of oscillation.
>
> >> > > > All that said, when I do an analysis of the filter using the z-
> >> > > > transform, I get a pole on the unit circle at 1,0 and a zero very
> >> > > > close to it at 0.999...,0. It would appear that the zero is
> >> > > > stabilizing the pole and frequencies other than very near DC.
> >> > > > But a DC input is stabilized by the overall loop. The question
> >> > > > is, how do I include the rest of the loop in a z-transform
> >> > > > analysis? Or is this not the right way to approach it?
>
> >> > > > Rick
>
> >> > > First clarification...when you say digital PLL, is this all in DSP,
> >> > > i.e. is it an NCO or a VCO with a real control voltage?
>
> >> > > The full loop is analyzed with the KVco the gain of the VCO (or
> >> > > NCO) and the gain of the phase detector. Since the VCO generates a
> >> > > frequency and the phase detector detects a phase, the combination
> >> > > produces a pole at DC or an integrator.
>
> >> > > Mark
>
> >> > All digital as in an FPGA. No VCO and no NCO, it uses a DCO. I was
> >> > mistaken when I used the term NCO.
>
> >> what's the difference between a Numerically-Controlled Oscillator and a
> >> Digitally-Controlled Oscillator?
>
> > I didn't think there was any, but it was explained to me that an NCO has
> > the lookup table to generate a sine/cosine output while a DCO just
> > provides either the upper bit to generate a square wave, or the carry
> > out to generate a one pulse per roll over. I used to use them
> > interchangeably, but I found this difference documented somewhere on the
> > web, so it must be true.
>
> >> > There is also an integrator in the filter. The filter integrator is
> >> > necessary to drive the error output of the phase comparator to zero.
>
> >> but there is also an inherent integrator in the DCO.
>
> > Yes, I wasn't trying to say this was different, just to get the
> > terminology correct. He was asking if it was a hardware VCO or
> > something else.
>
> >> > When you say the DCO and phase comparator produce a pole at DC, where
> >> > exactly is this DC determined? Are you referring to a DC input as in
> >> > 0 Hz? I believe if you have a 0 Hz input and your filter does not
> >> > include an integrator, the output will be 0 Hz. Am I missing
> >> > something?
>
> >> i am not sure if you're missing this or not, but in case you are,
> >> please lemme spell it out:
>
> >> 1. the output frequency of the DCO is presumed to be proportional to
> >> the input control paramenter.
>
> >> 2. frequency is the derivative of phase w.r.t. time. that means if you
> >> are going to relate *unwrapped* phase to frequency it's like the
> >> frequency parameter goes into an integrator and out comes phase.
>
> >> 3. the phase comparator compares the phase of the output of the DCO to
> >> the input waveform (which we assume is periodic) and gives you a result
> >> which is a number (or a pseudo-"voltage") which is proportional to that
> >> phase difference.
>
> >> 4. that phase difference is fed back through whatever gain and whatever
> >> other LTI system (or it might not all be linear, you might want to put
> >> some hard limiting in there or something else to help you hunt and lock
> >> when the frequencies are widely different). because in a discrete-time
> >> system we cannot have a closed loop with zero delay (we only know the
> >> previous output values to be used in the computation of the current
> >> input, we cannot know the current output for the current input), then
> >> there is necessarily a delay element in that feedback LTI system *must*
> >> have an overall 1/z factor in it.
>
> >> 5. so, even with the simplest proportional controller (no I or D in the
> >> PID), you will necessarily have an integrator (1/(1-1/z)) and another
> >> delay (1/z) in the loop. that cannot be avoided. now, if you choose
> >> to add more stuff than a P in your PID controller, you may, but your
> >> loop gain must have at least a 1/z * 1/(1-1/z) in it.
>
> >> dunno if any of this is helpful.
>
> >> r b-j
>
> > Thanks for the info. I am aware of everything you wrote. I just am
> > having trouble doing the math for it. My "filter" only needs an
> > integrator which will allow the error signal out of the phase detector
> > to become zero for any given frequency input. But this is not a stable
> > configuration. I added a proportional feedback which helps to stabilize
> > the loop. I can analyze the filter, but I'm not clear on how to analyze
> > the entire loop.
>
> Rick, can you clarify something please? Are you having a problem with
> the algebra, or are you having a problem with modelling the design?
>
> By "the algebra" I mean turning the transfer functions of the various
> parts (loop filter, nco, etc.) into a transfer function of the entire
> system.
>
> By "modelling the design", I mean turning your implementation of the
> various parts (e.g. adders, counters, accumulators, etc.) into transfer
> functions. If you haven't done this before, it may not be immediately
> obvious how to work out something like Kv for your NCO or the phase
> detector gain.
>
> Thanks,
> Allan

The modeling. I don't have trouble with algebra. I did retain that
bit from school.

I'm not worried about Kv or Kp. I am not clear on whether I should
treat which element as an integrator (the DCO clearly seems to be, but
I'm not sure about the phase comparator) and how to construct the
overall equation.

Rick

"rickman" <[email protected]> wrote in message
news:[email protected]...
> On May 30, 5:13 am, Allan Herriman <allanherri...@hotmail.com> wrote:
>> On Fri, 29 May 2009 21:57:44 -0700, rickman wrote:
>> > On May 29, 10:58 pm, robert bristow-johnson <r...@audioimagination.com>
>> > wrote:
>> >> On May 29, 6:53 pm, rickman <gnu...@gmail.com> wrote:
>>
>> >> > On May 29, 6:35 pm, makol...@yahoo.com wrote:
>>
>> >> > > On May 29, 6:15 pm, rickman <gnu...@gmail.com> wrote:
>>
>> >> > > > I posted a message a couple of months ago on a PLL I am working
>> >> > > > on, but I can't continue that thread. The circuit is using a
>> >> > > > PLL
>> >> > > > to generate an output clock which is a integer ratio multiple of
>> >> > > > the input clock. The purpose is to pull data out of a FIFO at
>> >> > > > the same rate it is going in and to keep a fixed amount of data
>> >> > > > in the FIFO while driving the output which is an interleave
>> >> > > > circuit. So the output clock needs to be N/(N-1) times the
>> >> > > > input
>> >> > > > clock and the PLL must maintain a zero phase relationship (long
>> >> > > > term) between the input clock and the divided down output clock
>> >> > > > in order to keep amount of data in the FIFO constant.
>>
>> >> > > > The circuit I came up with for this uses an up/down counter as
>> >> > > > the phase comparator. The the leading edge of the input clock
>> >> > > > makes it count up and the leading edge of the feedback clock
>> >> > > > makes it count down. If both occur during a given system clock
>> >> > > > cycle, the count is held as it is when there are no leading
>> >> > > > edges.
>>
>> >> > > > From what I have seen, this is considered a bang-bang phase
>> >> > > > comparator in the analog world. I guess it works the same in
>> >> > > > the
>> >> > > > digital world too. The filter I am using is an integrator added
>> >> > > > to a proportional (each with gain factors) to produce the step
>> >> > > > size fed to the NCO. The NCO produces a clock enable on
>> >> > > > overflow
>> >> > > > which feeds the interleave circuit. The interleave circuit
>> >> > > > returns N-1 out of every N clocks to pull data out of the FIFO
>> >> > > > and feedback to the PLL.
>>
>> >> > > > I simulated this with gain settings of A=64 for the proportional
>> >> > > > path and B=1/128 for the integrator output. I also tried other
>> >> > > > values and they are all stable, but some settle faster and
>> >> > > > others
>> >> > > > ring more before settling. I picked the values that seem to
>> >> > > > give
>> >> > > > me quick settling and track an input frequency change well
>> >> > > > without a lot of oscillation.
>>
>> >> > > > All that said, when I do an analysis of the filter using the z-
>> >> > > > transform, I get a pole on the unit circle at 1,0 and a zero
>> >> > > > very
>> >> > > > close to it at 0.999...,0. It would appear that the zero is
>> >> > > > stabilizing the pole and frequencies other than very near DC.
>> >> > > > But a DC input is stabilized by the overall loop. The question
>> >> > > > is, how do I include the rest of the loop in a z-transform
>> >> > > > analysis? Or is this not the right way to approach it?
>>
>> >> > > > Rick
>>
>> >> > > First clarification...when you say digital PLL, is this all in
>> >> > > DSP,
>> >> > > i.e. is it an NCO or a VCO with a real control voltage?
>>
>> >> > > The full loop is analyzed with the KVco the gain of the VCO (or
>> >> > > NCO) and the gain of the phase detector. Since the VCO generates
>> >> > > a
>> >> > > frequency and the phase detector detects a phase, the combination
>> >> > > produces a pole at DC or an integrator.
>>
>> >> > > Mark
>>
>> >> > All digital as in an FPGA. No VCO and no NCO, it uses a DCO. I was
>> >> > mistaken when I used the term NCO.
>>
>> >> what's the difference between a Numerically-Controlled Oscillator and
>> >> a
>> >> Digitally-Controlled Oscillator?
>>
>> > I didn't think there was any, but it was explained to me that an NCO
>> > has
>> > the lookup table to generate a sine/cosine output while a DCO just
>> > provides either the upper bit to generate a square wave, or the carry
>> > out to generate a one pulse per roll over. I used to use them
>> > interchangeably, but I found this difference documented somewhere on
>> > the
>> > web, so it must be true.
>>
>> >> > There is also an integrator in the filter. The filter integrator is
>> >> > necessary to drive the error output of the phase comparator to zero.
>>
>> >> but there is also an inherent integrator in the DCO.
>>
>> > Yes, I wasn't trying to say this was different, just to get the
>> > terminology correct. He was asking if it was a hardware VCO or
>> > something else.
>>
>> >> > When you say the DCO and phase comparator produce a pole at DC,
>> >> > where
>> >> > exactly is this DC determined? Are you referring to a DC input as
>> >> > in
>> >> > 0 Hz? I believe if you have a 0 Hz input and your filter does not
>> >> > include an integrator, the output will be 0 Hz. Am I missing
>> >> > something?
>>
>> >> i am not sure if you're missing this or not, but in case you are,
>> >> please lemme spell it out:
>>
>> >> 1. the output frequency of the DCO is presumed to be proportional to
>> >> the input control paramenter.
>>
>> >> 2. frequency is the derivative of phase w.r.t. time. that means if
>> >> you
>> >> are going to relate *unwrapped* phase to frequency it's like the
>> >> frequency parameter goes into an integrator and out comes phase.
>>
>> >> 3. the phase comparator compares the phase of the output of the DCO to
>> >> the input waveform (which we assume is periodic) and gives you a
>> >> result
>> >> which is a number (or a pseudo-"voltage") which is proportional to
>> >> that
>> >> phase difference.
>>
>> >> 4. that phase difference is fed back through whatever gain and
>> >> whatever
>> >> other LTI system (or it might not all be linear, you might want to put
>> >> some hard limiting in there or something else to help you hunt and
>> >> lock
>> >> when the frequencies are widely different). because in a
>> >> discrete-time
>> >> system we cannot have a closed loop with zero delay (we only know the
>> >> previous output values to be used in the computation of the current
>> >> input, we cannot know the current output for the current input), then
>> >> there is necessarily a delay element in that feedback LTI system
>> >> *must*
>> >> have an overall 1/z factor in it.
>>
>> >> 5. so, even with the simplest proportional controller (no I or D in
>> >> the
>> >> PID), you will necessarily have an integrator (1/(1-1/z)) and another
>> >> delay (1/z) in the loop. that cannot be avoided. now, if you choose
>> >> to add more stuff than a P in your PID controller, you may, but your
>> >> loop gain must have at least a 1/z * 1/(1-1/z) in it.
>>
>> >> dunno if any of this is helpful.
>>
>> >> r b-j
>>
>> > Thanks for the info. I am aware of everything you wrote. I just am
>> > having trouble doing the math for it. My "filter" only needs an
>> > integrator which will allow the error signal out of the phase detector
>> > to become zero for any given frequency input. But this is not a stable
>> > configuration. I added a proportional feedback which helps to
>> > stabilize
>> > the loop. I can analyze the filter, but I'm not clear on how to
>> > analyze
>> > the entire loop.
>>
>> Rick, can you clarify something please? Are you having a problem with
>> the algebra, or are you having a problem with modelling the design?
>>
>> By "the algebra" I mean turning the transfer functions of the various
>> parts (loop filter, nco, etc.) into a transfer function of the entire
>> system.
>>
>> By "modelling the design", I mean turning your implementation of the
>> various parts (e.g. adders, counters, accumulators, etc.) into transfer
>> functions. If you haven't done this before, it may not be immediately
>> obvious how to work out something like Kv for your NCO or the phase
>> detector gain.
>>
>> Thanks,
>> Allan
>
> The modeling. I don't have trouble with algebra. I did retain that
> bit from school.
>
> I'm not worried about Kv or Kp. I am not clear on whether I should
> treat which element as an integrator (the DCO clearly seems to be, but
> I'm not sure about the phase comparator) and how to construct the
> overall equation.
>
> Rick

Are you keeping track of the dimensional units? e.g., Kv and Kp have
units, usually something like V/rad or Hz/V for analog. I like to use
MSB/rad for a digital phase detector, as it allows characterization of the
gain and also provides a means to keep track of the precision through the
entire system (so that gain doesn't get screwed up due to a bit shift or
something).

If you do that it becomes pretty clear that most phase detectors aren't
integrators.

On May 30, 10:11*am, rickman <gnu...@gmail.com> wrote:
> On May 30, 5:13 am, Allan Herriman <allanherri...@hotmail.com> wrote:
>
>
>
> > On Fri, 29 May 2009 21:57:44 -0700, rickman wrote:
> > > On May 29, 10:58 pm, robert bristow-johnson <r...@audioimagination.com>
> > > wrote:
> > >> On May 29, 6:53 pm, rickman <gnu...@gmail.com> wrote:
>
> > >> > On May 29, 6:35 pm, makol...@yahoo.com wrote:
>
> > >> > > On May 29, 6:15 pm, rickman <gnu...@gmail.com> wrote:
>
> > >> > > > I posted a message a couple of months ago on a PLL I am working
> > >> > > > on, but I can't continue that thread. *The circuit is using a PLL
> > >> > > > to generate an output clock which is a integer ratio multiple of
> > >> > > > the input clock. *The purpose is to pull data out of a FIFO at
> > >> > > > the same rate it is going in and to keep a fixed amount of data
> > >> > > > in the FIFO while driving the output which is an interleave
> > >> > > > circuit. *So the output clock needs to be N/(N-1) times the input
> > >> > > > clock and the PLL must maintain a zero phase relationship (long
> > >> > > > term) between the input clock and the divided down output clock
> > >> > > > in order to keep amount of data in the FIFO constant.
>
> > >> > > > The circuit I came up with for this uses an up/down counter as
> > >> > > > the phase comparator. *The the leading edge of the input clock
> > >> > > > makes it count up and the leading edge of the feedback clock
> > >> > > > makes it count down. *If both occur during a given system clock
> > >> > > > cycle, the count is held as it is when there are no leading
> > >> > > > edges.
>
> > >> > > > From what I have seen, this is considered a bang-bang phase
> > >> > > > comparator in the analog world. *I guess it works the same in the
> > >> > > > digital world too. *The filter I am using is an integrator added
> > >> > > > to a proportional (each with gain factors) to produce the step
> > >> > > > size fed to the NCO. *The NCO produces a clock enable on overflow
> > >> > > > which feeds the interleave circuit. *The interleave circuit
> > >> > > > returns N-1 out of every N clocks to pull data out of the FIFO
> > >> > > > and feedback to the PLL.
>
> > >> > > > I simulated this with gain settings of A=64 for the proportional
> > >> > > > path and B=1/128 for the integrator output. *I also tried other
> > >> > > > values and they are all stable, but some settle faster and others
> > >> > > > ring more before settling. *I picked the values that seem togive
> > >> > > > me quick settling and track an input frequency change well
> > >> > > > without a lot of oscillation.
>
> > >> > > > All that said, when I do an analysis of the filter using the z-
> > >> > > > transform, I get a pole on the unit circle at 1,0 and a zero very
> > >> > > > close to it at 0.999...,0. *It would appear that the zero is
> > >> > > > stabilizing the pole and frequencies other than very near DC.
> > >> > > > But a DC input is stabilized by the overall loop. *The question
> > >> > > > is, how do I include the rest of the loop in a z-transform
> > >> > > > analysis? *Or is this not the right way to approach it?
>
> > >> > > > Rick
>
> > >> > > First clarification...when you say digital PLL, is this all in DSP,
> > >> > > i.e. is it an NCO *or a VCO with a real control voltage?
>
> > >> > > The full loop is analyzed with the KVco the gain of the VCO (or
> > >> > > NCO) and the gain of the phase detector. *Since the VCO generates a
> > >> > > frequency and the phase detector detects a phase, the combination
> > >> > > produces a pole at DC or an integrator.
>
> > >> > > Mark
>
> > >> > All digital as in an FPGA. *No VCO and no NCO, it uses a DCO. *I was
> > >> > mistaken when I used the term NCO.
>
> > >> what's the difference between a Numerically-Controlled Oscillator and a
> > >> Digitally-Controlled Oscillator?
>
> > > I didn't think there was any, but it was explained to me that an NCO has
> > > the lookup table to generate a sine/cosine output while a DCO just
> > > provides either the upper bit to generate a square wave, or the carry
> > > out to generate a one pulse per roll over. *I used to use them
> > > interchangeably, but I found this difference documented somewhere on the
> > > web, so it must be true.
>
> > >> > There is also an integrator in the filter. *The filter integrator is
> > >> > necessary to drive the error output of the phase comparator to zero.
>
> > >> but there is also an inherent integrator in the DCO.
>
> > > Yes, I wasn't trying to say this was different, just to get the
> > > terminology correct. *He was asking if it was a hardware VCO or
> > > something else.
>
> > >> > When you say the DCO and phase comparator produce a pole at DC, where
> > >> > exactly is this DC determined? *Are you referring to a DC input as in
> > >> > 0 Hz? *I believe if you have a 0 Hz input and your filter does not
> > >> > include an integrator, the output will be 0 Hz. *Am I missing
> > >> > something?
>
> > >> i am not sure if you're missing this or not, but in case you are,
> > >> please lemme spell it out:
>
> > >> 1. the output frequency of the DCO is presumed to be proportional to
> > >> the input control paramenter.
>
> > >> 2. frequency is the derivative of phase w.r.t. time. *that means if you
> > >> are going to relate *unwrapped* phase to frequency it's like the
> > >> frequency parameter goes into an integrator and out comes phase.
>
> > >> 3. the phase comparator compares the phase of the output of the DCO to
> > >> the input waveform (which we assume is periodic) and gives you a result
> > >> which is a number (or a pseudo-"voltage") which is proportional to that
> > >> phase difference.
>
> > >> 4. that phase difference is fed back through whatever gain and whatever
> > >> other LTI system (or it might not all be linear, you might want to put
> > >> some hard limiting in there or something else to help you hunt and lock
> > >> when the frequencies are widely different). *because in a discrete-time
> > >> system we cannot have a closed loop with zero delay (we only know the
> > >> previous output values to be used in the computation of the current
> > >> input, we cannot know the current output for the current input), then
> > >> there is necessarily a delay element in that feedback LTI system *must*
> > >> have an overall 1/z factor in it.
>
> > >> 5. so, even with the simplest proportional controller (no I or D in the
> > >> PID), you will necessarily have an integrator (1/(1-1/z)) and another
> > >> delay (1/z) in the loop. *that cannot be avoided. *now, if you choose
> > >> to add more stuff than a P in your PID controller, you may, but your
> > >> loop gain must have at least a 1/z * 1/(1-1/z) in it.
>
> > >> dunno if any of this is helpful.
>
> > >> r b-j
>
> > > Thanks for the info. *I am aware of everything you wrote. *I justam
> > > having trouble doing the math for it. *My "filter" only needs an
> > > integrator which will allow the error signal out of the phase detector
> > > to become zero for any given frequency input. *But this is not a stable
> > > configuration. *I added a proportional feedback which helps to stabilize
> > > the loop. *I can analyze the filter, but I'm not clear on how to analyze
> > > the entire loop.
>
> > Rick, can you clarify something please? *Are you having a problem with
> > the algebra, or are you having a problem with modelling the design?
>
> > By "the algebra" I mean turning the transfer functions of the various
> > parts (loop filter, nco, etc.) into a transfer function of the entire
> > system.
>
> > By "modelling the design", I mean turning your implementation of the
> > various parts (e.g. adders, counters, accumulators, etc.) into transfer
> > functions. *If you haven't done this before, it may not be immediately
> > obvious how to work out something like Kv for your NCO or the phase
> > detector gain.
>
> > Thanks,
> > Allan
>
> The modeling. *I don't have trouble with algebra. *I did retain that
> bit from school.
>
> I'm not worried about Kv or Kp. *I am not clear on whether I should
> treat which element as an integrator (the DCO clearly seems to be, but
> I'm not sure about the phase comparator) and how to construct the
> overall equation.
>
> Rick

In a mathematical PLL model, one typically derives H(z)=Y(z)/X(z)
where Y(z) is the phase of the input signal and X(z) is the phase of
the NCO. With this approach, the phase detector is just a scale
factor, P(z)=Kv. A PI loop filter can be modeled as F(z)=Kp*(1+Ki/
(z-1)). The NCO can be modeled as N(z)=z/(z-1).

The open loop TF is G(z)=Kv*F(z)*N(z)/z where the extra 1/z accounts
for computational delay as mentioned in another post. The closed loop
TF is H(z)=G(z)/(1+G(z)).

John

On Fri, 29 May 2009 15:15:38 -0700, rickman wrote:

> I posted a message a couple of months ago on a PLL I am working on, but
> I can't continue that thread. The circuit is using a PLL to generate an
> output clock which is a integer ratio multiple of the input clock. The
> purpose is to pull data out of a FIFO at the same rate it is going in
> and to keep a fixed amount of data in the FIFO while driving the output
> which is an interleave circuit. So the output clock needs to be N/(N-1)
> times the input clock and the PLL must maintain a zero phase
> relationship (long term) between the input clock and the divided down
> output clock in order to keep amount of data in the FIFO constant.
>
> The circuit I came up with for this uses an up/down counter as the phase
> comparator. The the leading edge of the input clock makes it count up
> and the leading edge of the feedback clock makes it count down. If both
> occur during a given system clock cycle, the count is held as it is when
> there are no leading edges.
>
> From what I have seen, this is considered a bang-bang phase comparator
> in the analog world.

I haven't seen the phrase "bang-bang" applied to a phase comparator. At
any rate, if your loop bandwidth is significantly less than your clock
rate the phase comparator reading will average out. Are you using the
count as your phase measurement, or just the last bit, or what?

If your goal is to maintain a nice FIFO fill level, why not use the FIFO
fill level as your phase comparator?

> I guess it works the same in the digital world
> too. The filter I am using is an integrator added to a proportional
> (each with gain factors) to produce the step size fed to the NCO. The
> NCO produces a clock enable on overflow which feeds the interleave
> circuit. The interleave circuit returns N-1 out of every N clocks to
> pull data out of the FIFO and feedback to the PLL.
>
> I simulated this with gain settings of A=64 for the proportional path
> and B=1/128 for the integrator output. I also tried other values and
> they are all stable, but some settle faster and others ring more before
> settling. I picked the values that seem to give me quick settling and
> track an input frequency change well without a lot of oscillation.
>
> All that said, when I do an analysis of the filter using the z-
> transform, I get a pole on the unit circle at 1,0 and a zero very close
> to it at 0.999...,0. It would appear that the zero is stabilizing the
> pole and frequencies other than very near DC. But a DC input is
> stabilized by the overall loop. The question is, how do I include the
> rest of the loop in a z-transform analysis? Or is this not the right
> way to approach it?

That is the right way to approach it. You need to model the behavior of
the phase comparator and the DCO in such a way that you can make z-domain
models of them. Then you can just put the loop together and see how it
looks.

If you take the input to the DCO to be the desired frequency (or phase
increment, or target count), and the output to be the phase (or timing)
offset, then the DCO will act like an integrator -- so you can treat it
as having an action k_o / (z - 1). Finding k_o will be interesting, in
no small part because it depends on how you define your inputs and
outputs. Your best bet will be to fit the behavior to an integrator with
a gain of the right dimensions, then figure out the value of the
integrator gain.

Some DCO arrangements will be nonlinear. Specifically, if you use a
simple count-to-value-and-reset, or load-value-and-reload-at-zero, then
the frequency will be the reciprocal of the command. You'll have to
linearize this by taking the derivative of the frequency with respect to
the command at the nominal rate. Ask here if that's the case...

Ditto with your phase comparator. It will respond to the phase of the
DCO with a linear relationship, so you can model it as a simple gain
(call it k_phi).

Once you have those two models, then you can model your whole loop. This
loop model will look an awful lot like loop models for analog PLLs, so
you could do a lot worse than to search around the web for basic PLL
discussions. I'd suggest a book such as http://www.powells.com/
partner/30696/biblio/0136627439, except that it is entirely oriented
toward analog PLLs, so you only want it if you feel confident in
translating everything to digital.

If I haven't lost enough shame to suggest it already, you may also want a
copy of my book: http://www.wescottdesign.com/actfes/actfes.html. It
doesn't go into PLLs specifically, but it certainly gives you some strong
background in control theory.

--
http://www.wescottdesign.com

On May 30, 12:40*pm, Tim Wescott <t...@seemywebsite.com> wrote:
> On Fri, 29 May 2009 15:15:38 -0700, rickman wrote:
> > I posted a message a couple of months ago on a PLL I am working on, but
> > I can't continue that thread. *The circuit is using a PLL to generatean
> > output clock which is a integer ratio multiple of the input clock. *The
> > purpose is to pull data out of a FIFO at the same rate it is going in
> > and to keep a fixed amount of data in the FIFO while driving the output
> > which is an interleave circuit. *So the output clock needs to be N/(N-1)
> > times the input clock and the PLL must maintain a zero phase
> > relationship (long term) between the input clock and the divided down
> > output clock in order to keep amount of data in the FIFO constant.
>
> > The circuit I came up with for this uses an up/down counter as the phase
> > comparator. The the leading edge of the input clock makes it count up
> > and the leading edge of the feedback clock makes it count down. *If both
> > occur during a given system clock cycle, the count is held as it is when
> > there are no leading edges.
>
> > From what I have seen, this is considered a bang-bang phase comparator
> > in the analog world.
>
> I haven't seen the phrase "bang-bang" applied to a phase comparator. *At
> any rate, if your loop bandwidth is significantly less than your clock
> rate the phase comparator reading will average out. *Are you using the
> count as your phase measurement, or just the last bit, or what?
>
> If your goal is to maintain a nice FIFO fill level, why not use the FIFO
> fill level as your phase comparator?

BINGO! You win the cupie doll! That *is* what I am using, the fifo
fill counter offset so that it is zero at the proper fill level. The
idea is that by using an integrator in the filter section, the error
term will return to zero and the FIFO level will be restored.

The entire count is used, but in my simulations I only saw the value
range less than 100 +- and I think it was much less depending on the
coefficients on the proportional and integrator terms.


> > I guess it works the same in the digital world
> > too. *The filter I am using is an integrator added to a proportional
> > (each with gain factors) to produce the step size fed to the NCO. *The
> > NCO produces a clock enable on overflow which feeds the interleave
> > circuit. *The interleave circuit returns N-1 out of every N clocks to
> > pull data out of the FIFO and feedback to the PLL.
>
> > I simulated this with gain settings of A=64 for the proportional path
> > and B=1/128 for the integrator output. *I also tried other values and
> > they are all stable, but some settle faster and others ring more before
> > settling. *I picked the values that seem to give me quick settling and
> > track an input frequency change well without a lot of oscillation.
>
> > All that said, when I do an analysis of the filter using the z-
> > transform, I get a pole on the unit circle at 1,0 and a zero very close
> > to it at 0.999...,0. *It would appear that the zero is stabilizing the
> > pole and frequencies other than very near DC. *But a DC input is
> > stabilized by the overall loop. *The question is, how do I include the
> > rest of the loop in a z-transform analysis? *Or is this not the right
> > way to approach it?
>
> That is the right way to approach it. *You need to model the behavior of
> the phase comparator and the DCO in such a way that you can make z-domain
> models of them. *Then you can just put the loop together and see how it
> looks.
>
> If you take the input to the DCO to be the desired frequency (or phase
> increment, or target count), and the output to be the phase (or timing)
> offset, then the DCO will act like an integrator -- so you can treat it
> as having an action k_o / (z - 1). *Finding k_o will be interesting, in
> no small part because it depends on how you define your inputs and
> outputs. *Your best bet will be to fit the behavior to an integrator with
> a gain of the right dimensions, then figure out the value of the
> integrator gain.
>
> Some DCO arrangements will be nonlinear. *Specifically, if you use a
> simple count-to-value-and-reset, or load-value-and-reload-at-zero, then
> the frequency will be the reciprocal of the command. *You'll have to
> linearize this by taking the derivative of the frequency with respect to
> the command at the nominal rate. *Ask here if that's the case...

I'm not sure what you mean in this paragraph. The DCO is just an
accumulator. The output of the filter is the step size, or as you
say, the frequency. This is repeatedly added to the value in the
accumulator and when it rolls over, the carry out is used as a clock
enable which is the clock output. The filter output is *NOT* being
used as the max value in a counter. That would invert the sense and
as you say, make it non-linear.


> Ditto with your phase comparator. *It will respond to the phase of the
> DCO with a linear relationship, so you can model it as a simple gain
> (call it k_phi).

Yes, I get that now. Although it has a delay, so there is a z term
associated with it.


> Once you have those two models, then you can model your whole loop. *This
> loop model will look an awful lot like loop models for analog PLLs, so
> you could do a lot worse than to search around the web for basic PLL
> discussions. *I'd suggest a book such ashttp://www.powells.com/
> partner/30696/biblio/0136627439, except that it is entirely oriented
> toward analog PLLs, so you only want it if you feel confident in
> translating everything to digital.
>
> If I haven't lost enough shame to suggest it already, you may also want a
> copy of my book: *http://www.wescottdesign.com/actfes/actfes.html. *It
> doesn't go into PLLs specifically, but it certainly gives you some strong
> background in control theory.
>
> --http://www.wescottdesign.com

Thanks, I tried to order the book using a discount code and it didn't
apply the code after it said the discount would be applied at
checkout. I wrote them. If they can get this fixed, I will order the
book.

Rick