FPGA Central

Hi,
I have a little problem addressing data.Take a look on this part of code:


SCRAMBLER:
/***** FIRST PART *******/
i4 = Input_Real;
i0 = FFT_IO_Real;
m4 = 1;
m0 = Mod_Value; // Mod_Value = 2 ^ 14-log2 (N)
l4 = 0;
l0 = 0;

CNTR = N;
ENA BIT_REV;
DO SR_Loop UNTIL CE;
ay1 = DM(i4,m4); // Reversing Real part
SR_Loop: DM(i0,m0) = ay1;
DIS BIT_REV;

/***** SECOND PART *******/
i4 = Input_Image;
i0 = FFT_IO_Image;
m4 = 1;
m0 = Mod_Value;
l4 = 0;
l0 = 0;

CNTR = N;
ENA BIT_REV;
DO SI_Loop UNTIL CE;
ay1 = DM(i4,m4); //Reersing image part
SI_Loop: DM(i0,m0) = ay1;
DIS BIT_REV;
rts;

It's the scramble function before executing FFT ,

The problem is: the data it's correcty moving from "Input_Real" table
into "FFT_OI_Real" table. ( the first part ) but at the second part, when
the data from
"Input_Image" should be transferred into "FFT_IO_Image" the data is
transferred into
"Input_Real" WHY ??
The tables are declarated as:

..SECTION/DM sound_data;

..VAR/CIRC Input_Real[N];
..VAR/CIRC Input_Image[N];

..VAR/CIRC FFT_IO_Real[N];
..VAR/CIRC FFT_IO_Image[N];

where N=64;

What is wrong ??

If someones could be so kindly and find a minute for me, I can send a full
code via email
( it's really short , and its for Visual DSP , and for 2181 simulation) It
will be very helpfull for me.