FPGA Central

Hi all,
I want to implement soft decision viterbi decoder in FPGA. I have alread
implemented hard-decision decoding and the design works fine in xilin
FPGA. We have implemented "high bit clear circuit" for path metric
normalization to reduce the area.

Now, i want to implement soft-decision decoding an I need to change th
BMU and ACS modules in my code.

One thing that worries me is the normalization technique that can be use
for soft-decision viterbi. since the calculation of euclidean distance wil
result in negative numbers many times, i can't use "high bit clear circuit
that i have used for hard-decision. So what normalization technique o
methodology, I can use for implementing ACS block in soft-decisio
viterbi.

Thanks all!