FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > DSP

DSP comp.dsp newsgroup, mailing list

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 06-27-2003, 08:11 PM
Dave F
Guest
 
Posts: n/a
Default 6711 DSK linker cmd file

Hey guys,

Is there any way to tell the code composer studio to make
a chunk in off-chip ram CE0, and just put 2 arrays in it?
I dont want to put all my data variables in it, since it
is slower than IRAM and this is a real-time DSP app.

Thanks
Dave
Reply With Quote
  #2 (permalink)  
Old 06-30-2003, 06:30 AM
Jerry J. Trantow
Guest
 
Posts: n/a
Default Re: 6711 DSK linker cmd file

"Dave F" <[email protected]> wrote in message
news:LN%Ka.518$[email protected]..
> Hey guys,
>
> Is there any way to tell the code composer studio to make
> a chunk in off-chip ram CE0, and just put 2 arrays in it?
> I dont want to put all my data variables in it, since it
> is slower than IRAM and this is a real-time DSP app.
>
> Thanks
> Dave


This is relatively easy to do.

1) Use the #pragmas to place specified variables into certain sections.
2) Add a section to your .cmd to put the section into the desired memory
block.

/*
Put this at the top of your C code.
Make sure you don't include an extern to this variable above the #pragma
statement. (Sometimes happens if you include a header file.)
*/
#pragma DATA_SECTION(sine_table, "tables")
COMPLEX sine_table[N]; // Stores cosine and sine values for lookup.

/*
Linker.cmd.
*/
SECTIONS {
coeff_sect > SARAM_A
samples >SARAM
tables > SARAM_B
}



Reply With Quote
  #3 (permalink)  
Old 06-30-2003, 10:13 AM
John McCabe
Guest
 
Posts: n/a
Default Re: 6711 DSK linker cmd file

On Sun, 29 Jun 2003 23:30:05 -0500, "Jerry J. Trantow"
<[email protected]> wrote:

>/*
> Put this at the top of your C code.
> Make sure you don't include an extern to this variable above the #pragma
>statement. (Sometimes happens if you include a header file.)
>*/
>#pragma DATA_SECTION(sine_table, "tables")
>COMPLEX sine_table[N]; // Stores cosine and sine values for lookup.


Note that pragma DATA_SECTION has a slightly different syntax if
you're using C++! In C++ the pragma is not qualified with an object
name, and is applicable to only the object immediately following the
pragma. So, for the above, you would just have:

#pragma DATA_SECTION("tables")
COMPLEX sine_table[N]; // Stores cosine and sine values for lookup.


Best Regards
John McCabe

To reply by email replace 'nospam' with 'assen'
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
a question about linker map file [email protected] FPGA 2 07-18-2008 12:45 PM
6711 Memory Dave F DSP 5 04-25-2006 03:59 AM
Xilinx mb-gcc, linker scripts and splitting Object-file sections Ruediger Scheidig FPGA 0 05-26-2004 12:38 PM
6711 DSK Memory Question Dave F DSP 1 06-25-2003 12:00 PM


All times are GMT +1. The time now is 01:41 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved