Allan Herriman <
[email protected]> writes:
> On Fri, 24 Dec 2004 15:25:23 GMT, Randy Yates <
[email protected]> wrote:
>
>>
[email protected] (Jrferguson) writes:
>>
>>> I am trying to locate tutorial information on pipelined ADCs, without any
>>> success as yet. I would very grateful for any pointers that readers may be able
>>> to provide.
>>
>>Pipelines are to paralellize things like instruction accesses,
>>decoding, execution, etc. None of these occur in an A/D.
>>
>>Are you thinking perhaps of multiplexing A/Ds that use multiple samplers
>>to get higher sampling rates?
>
> Randy, you seem to have missed a revolution in high speed ADC design
> from, umm, about a decade ago.
>
> Pipelined converters allow high resolution (12-14 bits) at high sample
> rates (~100Msps). No other converter architecture comes close (Flash
> can be faster, but only at low resolutions). The development of
> pipelined converters has enabled the ADC to move "closer to the
> antenna" in digital radio designs. (I'm not sure which was the cause,
> and which was the effect - pipelined converters and digital radio go
> hand-in-hand.)
>
>
> The problem with a Flash converter is that the number of comparators
> increases exponentially with the number of bits. This limits the
> number of bits to about 10.
>
> To increase the number of bits further, we can use N (typically 2 or
> 3) lower resolution flash converters. The output of the first
> converter is sent to a DAC. The output of the DAC is subtracted from
> the input signal, and this residue is then amplified and sent to the
> next identical stage in the pipeline. Typically there is a sample and
> hold between each stage in the pipeline.
>
> This results in a circuit size that grows roughly linearly with the
> number of bits, instead of exponentially.
>
> The individual Flash converters and DACs in the pipeline stages don't
> need many bits (typically 6), but the first stage needs to have an
> *accuracy* determined by the total number of bits being generated.
>
> About the only disadvantage of pipelined converters is the pipeline
> delay, which may be an issue if the ADC is in a feedback loop.
It is clear that I had a gap in my understanding on this topic,
Allan. Thank you for giving me a heads-up and a quick education.
I also apologize to Jrferguson (and anyone else read and was misled)
for giving wrong information.
However, Allan, could I ask you to please do one thing? Refrain from
using the "umm" idiom when you write usenet posts unless your
intention is to disrepect the poster.
--
% Randy Yates % "She's sweet on Wagner-I think she'd die for Beethoven.
%% Fuquay-Varina, NC % She love the way Puccini lays down a tune, and
%%% 919-577-9882 % Verdi's always creepin' from her room."
%%%% <
[email protected]> % "Rockaria", *A New World Record*, ELO
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