On Aug 30, 2:02*pm, David Bishop <
[email protected]> wrote:
> Andy wrote:
> > On Aug 29, 4:22 pm, Mike Treseler <
[email protected]> wrote:
> >> move wrote:
> >>> how to get the right answer?
> >> That is an interesting question.
>
> >> To synthesize any significant signed math,
> >> I make an rtl-style sim model using reals to work
> >> out all the register lengths.
>
> >> To check the sims, I might also use thiswww.python.org/download
> >> as a functional calculator.
>
> >> Once the real answers are right in simulation,
> >> I convert the reals to integer ranges
> >> for small numbers, or to numeric_std.signed
> >> vectors for big numbers.
>
> >> * * * * -- Mike Treseler
>
> > There is a new standard package for fixed point, that does not
> > overflow or roll over, the result is large enough to handle the
> > largest possibility (n+1 bits in the case of adding or subtracting n
> > bit operands). Just declare a signed fixed point vector with zero
> > fractional bits, and you have mathematically accurate integer
> > arithmetic, but you have to keep up with the signal/variable widths
> > yourself (the compiler keeps you honest).
>
> This issue is exactly the reason that the fixed point package grows one
> bit when it does an "abs" or a "-" on a number. * When writing your code
> it drives you nuts, but it keeps the precision correct.
>
> You can get this package (downgraded for vhdl-93) at:http://www.vhdl.org/fphdl/vhdl.html
Yes, declaring signals and variables of the correct size to handle the
results is a pain, but it keeps you aware of what is going on. The
functions help, but are still not very easy to use. This is (at
least) one place where I wish you could declare an unconstrained
variable, initialized to its appropriate width as follows:
variable a,b : sfixed(7 downto 0):= (others => 0);
variable ab_sum : sfixed := a + b;
You can do that with constants...
Andy