On Jun 22, 3:25 pm, "Macias Wojtas" <
[email protected]> wrote:
> > We have just released a plugin for eclipse which supports VHDL. It
> > supports all of the basic editting functionallity with numerous
>
> I tried it with your example project and it looks fine. I use opensource
> eclipse plag-in for VHDL/Verilog 'veditor'.
>
> It has some futures which I couldn't find in your plugin:
>
> - block comment
>
> - interface to another tools for error correction - in veditor u can use eg
> ModelSim to highlight your syntax error.
>
> Code Completion works really good, but why it not suggests types of signal,
> variables, constants (eg. When u are using use std_logic_1164 it could
> suggest STD_LOGIC)
>
> PS It is really good and useful tool :)
>
> Best regards
>
> Maciek Wojtynski
Maciek,
Thanks for the response. We really appreciate feedback as we are
working hard to improve this tool.
As to your feature questions :
1. Block Comment/Uncomment is actually supported in the editor context
window. It should show up in the popup menu when if you right click.
This popup window also contains a few other actions which are
"reference" which does a context based search along with refactor -
>rename which does a context based rename.
2. std_logic and std_logic vector should be part of the completion if
std_logic_1164 is in context. They are not templates but should be
found in the package. If you hit Ctrl+Space and start type std...
std_logic and std_logic_vector should appear in the completion
window.
3. Interfaces to other tools is very high on our priority list, and
will definitely be added in the near future. Syntax errors and a few
other types of errors are actually currently highlighted by the
plugin, but we would like to support not only simulation tools but
synthesis, formal verification and ... tools.
Again thanks for the comments and please feel free to contact us with
any issues, general comments, or feature requests as we are attempting
to improve this tool.
Thanks,
Andy Wagner
[email protected]