View Full Version : a self study project VHDL + specman

02-09-2012, 08:03 AM
Based on a VHDL simple UART, I created a small verification eVC.
The DUT was first tested, using GHDL and the VHDL code and scripts can be taken from this location - UART DUT

This project consists of three main parts. Unit level check for the UART TX and RX. Then the DUT RX and TX are connected and tested. The later reuses both RX and TX eVC(s).
It is shown how to connect and configure the two separate eVC(s) in the full chip environment.

If you would like to be notified on any changes done on this project, please send me an email. Put UART specman in the mail subject....