10-07-2009, 10:15 PM
Hello
Learn about the latest in tools for FPGA Design and
Verification. If making sure that your safety-critical
designs are up to expectations is your goal, then check out
our webinar series on Ensuring Safe Design.
---------------------------------------------------------
IN THIS ISSUE:
> Technical Paper
> Web Seminar Series (Live and On-Demand)
> News/Press
> Mentor Communities
---------------------------------------------------------
> Technical Paper
* Diagnosing CDC Errors in FPGAs
Clock domain crossing (CDC) errors in FPGAs are
elusive, and locating them often requires good
detective work and smart design as well as an
understanding of metastability and other physical
behaviors. This white paper discusses the nature of CDC
errors and presents a powerful solution that aids in
their detection and removal. You can join the
discussion forum on this topic at Mentor Communities
(http://lyris.mentor-info.com/t/28040/11468829/13066/3871/).
http://lyris.mentor-info.com/t/28040/11468829/13067/3872/
> Web Seminar Series (Live and On-Demand)
* Ensuring Safe Design: FPGA Synthesis for Design
Assurance in Mil-Aero & Safety Critical Applications
Join Mentor Graphics in this web seminar series,
available both live and on-demand, which introduces new
design assurance tools and features that will give you
the control to adequately guard against design faults,
preserve design functionality, and track design
requirements through the synthesis and place & route
flow. Learn more about these new capabilities in FPGA
synthesis for mil-aero and safety critical
applications:
- Fault Tolerant FSM Design
- Triple Mode Redundancy (TMR) in Synthesis
- Formal Verification of Advanced Synthesis
Optimizations
- Requirements Tracing through Synthesis
More information
http://lyris.mentor-info.com/t/28040/11468829/13068/3764/
> News/Press
* Tool Up for the FPGA Blitz
Thanks to the growth in their capabilities (and in
ASIC/SoC mask costs), FPGAs are enjoying a new surge in
popularity. Here's a look at the latest in tools for
FPGA design and verification.
http://lyris.mentor-info.com/t/28040/11468829/13070/3873/
> Mentor Communities
Want to find out how others are tackling design issues
or have questions that other engineers might help answer?
Then join the new ASIC/FPGA web communities offering
discussion forums where you can gain insights from other
members and share your expertise
Just use your SupportNet log-in to register. If you do
not have a SupportNet login, joining the communities is
quick and simple.
Join the ASIC/FPGA Community
http://lyris.mentor-info.com/t/28040/11468829/13071/3261/
Have a friend or colleague that would like this
newsletter?
Feel free to pass it on!
---------------------------------------------------------
Simon Bloch
Vice President and General Manager, DCS Division
Mentor Graphics Corporation
http://lyris.mentor-info.com/t/28040/11468829/13072/2736/
Email: fpga_news (AT) mentor (DOT) com
---------------------------------------------------------
If you do not wish to receive future FPGA Tech News
updates, please update your subscription at:
http://www.mentor.com/updates/fpganews.cfm?email=newsletter (AT) list (DOT) fpgacentral.com&action=r
Mentor Graphics 8005 SW Boeckman Rd, Wilsonville, OR 97070
United States
800-547-3000 or 503-685-8000
Learn about the latest in tools for FPGA Design and
Verification. If making sure that your safety-critical
designs are up to expectations is your goal, then check out
our webinar series on Ensuring Safe Design.
---------------------------------------------------------
IN THIS ISSUE:
> Technical Paper
> Web Seminar Series (Live and On-Demand)
> News/Press
> Mentor Communities
---------------------------------------------------------
> Technical Paper
* Diagnosing CDC Errors in FPGAs
Clock domain crossing (CDC) errors in FPGAs are
elusive, and locating them often requires good
detective work and smart design as well as an
understanding of metastability and other physical
behaviors. This white paper discusses the nature of CDC
errors and presents a powerful solution that aids in
their detection and removal. You can join the
discussion forum on this topic at Mentor Communities
(http://lyris.mentor-info.com/t/28040/11468829/13066/3871/).
http://lyris.mentor-info.com/t/28040/11468829/13067/3872/
> Web Seminar Series (Live and On-Demand)
* Ensuring Safe Design: FPGA Synthesis for Design
Assurance in Mil-Aero & Safety Critical Applications
Join Mentor Graphics in this web seminar series,
available both live and on-demand, which introduces new
design assurance tools and features that will give you
the control to adequately guard against design faults,
preserve design functionality, and track design
requirements through the synthesis and place & route
flow. Learn more about these new capabilities in FPGA
synthesis for mil-aero and safety critical
applications:
- Fault Tolerant FSM Design
- Triple Mode Redundancy (TMR) in Synthesis
- Formal Verification of Advanced Synthesis
Optimizations
- Requirements Tracing through Synthesis
More information
http://lyris.mentor-info.com/t/28040/11468829/13068/3764/
> News/Press
* Tool Up for the FPGA Blitz
Thanks to the growth in their capabilities (and in
ASIC/SoC mask costs), FPGAs are enjoying a new surge in
popularity. Here's a look at the latest in tools for
FPGA design and verification.
http://lyris.mentor-info.com/t/28040/11468829/13070/3873/
> Mentor Communities
Want to find out how others are tackling design issues
or have questions that other engineers might help answer?
Then join the new ASIC/FPGA web communities offering
discussion forums where you can gain insights from other
members and share your expertise
Just use your SupportNet log-in to register. If you do
not have a SupportNet login, joining the communities is
quick and simple.
Join the ASIC/FPGA Community
http://lyris.mentor-info.com/t/28040/11468829/13071/3261/
Have a friend or colleague that would like this
newsletter?
Feel free to pass it on!
---------------------------------------------------------
Simon Bloch
Vice President and General Manager, DCS Division
Mentor Graphics Corporation
http://lyris.mentor-info.com/t/28040/11468829/13072/2736/
Email: fpga_news (AT) mentor (DOT) com
---------------------------------------------------------
If you do not wish to receive future FPGA Tech News
updates, please update your subscription at:
http://www.mentor.com/updates/fpganews.cfm?email=newsletter (AT) list (DOT) fpgacentral.com&action=r
Mentor Graphics 8005 SW Boeckman Rd, Wilsonville, OR 97070
United States
800-547-3000 or 503-685-8000