Re: Board layout for FPGA
On Feb 5, 5:15*am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk > wrote:
> > John,
> > I don't think I can get away with only the outer two rows of balls,
> > I'll probably need the two inside of that as well-- I was thinking of
> > breaking out the outer two on one signal layer and the inner two in
> > another, as suggested in the Xilinx app note I saw. It was a tight
> > squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
> > is the standard offering of the board house we're using.. it's
> > possible to ask for smaller, for an extra chunk of change.
>
> With 1mm ball pitch I use 0.5mm pads, 0.5mm vias with 0.25mm drills.
>
> This is pretty much run of the mill for fab houses and shouldn't
> add much to costs.
0.25 mm drill is 10 mil. I have had fab houses say they can't do 10
mil. One in particular applied a "standard" rule of +- 3 mil
tolerance and used a 13 mil drill without telling me. Of course,
without saying any names, I don't use Sunstone anymore. ;^) (They
also had a >20% Xout rate on that run and had to do a second run to
get me the last panel, not that I would ever bad mouth them...)
The lower limit for the lower end board houses (in terms of costs not
quality) tends to be around 15 mil. I don't think you can do any of
these BGAs using 15 mil vias, so the truly low end houses are likely
out anyway. It is important to choose a *good* fab house. I have
found quality to vary a *lot*.
Rick
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