> Now that I think of it, I suppose I could make the bus connection job
> a little simpler if I take advantage of the fact that RAM is "random
> access," so the address/data line numbers from chip to chip don't
> necessarily have to match up. Then the address/data lines could be
> connected in whatever order is easiest and cleanest, since on the FPGA
> side the data would go in and come out in the desired order either
> way.
> Would this for any reason be a bad design practice?


Cypress don't even define address and data pin numbers for their synchronous
rams (apart from A0 and A1).

Go for it.


Nial