On Feb 4, 9:43*pm, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:
> > Are there any examples out there of how to route memory chips on a
> > bus? I'm kind of new to routing and don't really know what the
> > strategy is for this kind of thing. I was thinking about this when
> > designing a board to interface to expansion headers on a dev board for
> > a first prototype, but I couldn't think of a way to do it with just
> > two layers, so I gave each chip its own lines in that case since I had
> > plenty of I/O.
>
> Now that I think of it, I suppose I could make the bus connection job
> a little simpler if I take advantage of the fact that RAM is "random
> access," so the address/data line numbers from chip to chip don't
> necessarily have to match up. Then the address/data lines could be
> connected in whatever order is easiest and cleanest, since on the FPGA
> side the data would go in and come out in the desired order either
> way.
> Would this for any reason be a bad design practice?
>
> Steve

In response to your other post about the bus timing, async memories
are the hardest to design I have found. Sync memories like SDRAM are
a snap really, you just meet the setup and hold times and you are
done! The rest is all just a state machine. Async busses require all
sorts of timing numbers to be checked, I bet you will have over 30
numbers you will need to validate while doing this. If you don't push
the timing to the max it can be much easier.

As to the randomization of the address/data lines, I have never done
that, but others have. On the RAMs it shouldn't be a problem. It
can even be worked around on the EEPROM if you have a program to remap
all the bits in the memory map, but that is such a PITA. Getting your
schematic to optimize the layout without randomization of the lines
shouldn't be a real problem.

Rick