On Feb 4, 5:28 am, Symon <symon_bre...@hotmail.com> wrote:
> On 2/4/2010 8:23 AM, David Brown wrote:
>
>
>
>
>
> > You have a lot more experience at this sort of thing than me, Rick, so
> > I'm a little wary of disagreeing with you. But I'm sure you'll tell me
> > if I get something wrong!
>
> > I don't see that you have to worry about any termination here. With fast
> > enough signal edges, you can get ringing - but that typically will not
> > matter because you don't sample the signals until the ringing has
> > subsided.
>
> > Ringing can cause a few problems - the overshoot/undershoot can go
> > outside the voltage range of the pins on the line, it can cause
> > interference for neighbouring signals, you can't read the signal while
> > it is ringing, and it can cause big trouble when connected to
> > edge-sensitive inputs. But most of these are not going to be a problem
> > in your case, I think.
>
> Dear David, Steve,
>
> Going "outside the voltage range of the pins on the line" can break the
> device. IIRC there are Xilinx appnotes which go into this problem in
> some detail; powering 3.3V with 3V was something I think they suggested!
> (See XAPP653)
> Also, the thing will probably fail any sort on electromagnetic
> compliance test that you would need to do before you sell this. And you
> are unlikely to be able to listen to 'The Archers' while this thing is
> in the room.
>
> To the OP, in the absence of micro-vias, I would recommend a 6 layer
> board. Maybe like this:-
>
> signal
> signal
> ground
> ground
> power/signal
> signal
>
> Keep all the layers as close together as your PCB manufacturer allows
> and make up the board thickness with the core between the two ground
> layers. Xilinx on the top. Route the powers, or use copper pours. Try to
> make room for bypass caps on the back of the board from the FPGA. This
> stack up will make it very difficult for a beginner to go wrong from an
> SI point of view, as ground is always near. This is particularly true if
> you have a nice spread of ground vias tying the two ground planes
> together. That doesn't mean you shouldn't simulate it with Hyperlynx,
> but I bet that won't happen! Always examine your ground plane pair at
> the end of the routing process to make sure you haven't cut any big
> slots in it with string of vias.
>
> Finally, _real_ engineers use DRAMs! ;-)
>
> HTH., Syms.
>
> p.s. Did I make it clear that the ground is important?

Everyone has their own way of doing things, but I would ask, why the
two ground planes? I would have a ground plane and a power plane in
the center with a minimum thickness between them. The spacing between
the ground/power plane and the signal plane is not so important. What
is important is the characteristic impedance. The lower the
impedance, the less it will radiate. Of course, with thin traces you
have to have the signal plane to power/ground plane very small to get
a low impedance. But if you have wide traces, you can open up the
plane spacing. Since the outer layers are on the outside of the
board, they won't be very close to inside power/ground planes. BTW,
you are aware that the power plane is just as effective as the ground
plane for determining the impedance.

Rick