On Feb 4, 4:04*am, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:
> Thanks for the input so far, guys!
>
> I will have two SRAM chips and one parallel EEPROM in one memory
> space, and one additional RAM chip in a separate memory space so I
> know for sure that that one gets its own dedicated address/control/
> data lines.
> I was just wondering if the signal integrity would be hurt by extra
> loading in chaining up the ones that are on the same bus, but I had a
> hunch that at these speeds it wouldn't be such a big problem.

Signal integrity is not normally a direct result of the "loading" of
the parts. On most boards the effect of a pin on a bus is minimal.
If you split a run, like a fork in a river, it results in an impedance
mismatch and causes a reflection. The end of a trace is a high
impedance which also is an impedance mismatch and causes a
reflection. Three chips can be added to the board with trances as
short as maybe 2 inches. This is 4 inches round trip or about half a
ns. To avoid effects of reflection, the edge transition time should
be at least 3 ns. That is a *slow* edge. So expect noticeable
ringing. As has been said, on the data and address lines, you just
need to extend the setup times to wait it out to sample the bus when
it has quieted down. Figure three round trips or 1.5 ns extra. But
the write enable signal should be clean. The best way I know to do
that is to provide a separate write enable driver for each chip. Then
you can use series impedance matching in a point to point wiring so
that the receiver does not see any effects from reflection. Of course
this is assuming the write enable is the controlling pin when doing
writes. Some designs use the chip select to control the write
timing.


> And probably I will be using 10ns RAMs (I haven't looked at the rise/
> fall times though) and keeping them physically as close as I can get
> them to the FPGA.. maybe about a centimeter away, tops.
> Looking at this old Digilent Spartan 3 board I have kicking around, I
> don't see any termination between the FPGA and the ISSI SRAMs on
> there, but each chip has its own address and data lines.. I dunno if
> that's good enough to use as an example or not though.

Are you going to try to use them as fast as possible? That can be
hard. If you can give each chip separate drivers for all signals, may
be able to keep the traces short enough to not see any reflection
effects. I may have muffed the math on this. That's the trouble with
rules of thumb. If you recall them incorrectly, it can be hard to
spot the error. Looking at this document,

http://techcircuits.net/docs/CriticalLength.pdf

It looks like I was overly pessimistic on the length. The rule of
thumb seems to be 1/3 instead of 1/6 so a 1 ns rise time won't cause
significant reflections, but I'm not sure about that. On page 7 they
use an analysis that I don't agree with. Basically, they are saying
this is the critical edge of timing and I don't think it is that clear
cut. I say use 1/6, but you can choose your own poison.


> As for the supply voltages, I'll be using a Virtex II, but this is the
> first time I have started to think about implementing my own board and
> thus needing to worry about power supplies, and I seemed to remember
> some of my dev boards in the past having a couple or three different
> regulators on board, but I didn't really think much about it. Looking
> at the datasheet though, you're right, Rick, it appears that I just
> need a single 1.5V supply for core voltage, and 3.3V for VCC_aux and
> all of my I/O. I should have checked that and had the numbers right
> before asking, sorry about that.

I would pick a newer family myself, but there is nothing wrong with a
Virtex II device. However, a newer family will be faster, lower power
and you will likely get better support. Of course you can overdo that
too. If you try to use the newest family, you may not get parts for
months and the tools may be a bit buggy... But Virtex 2??? Why not
Virtex 5 or even Virtex 4? The Spartan 3 chips are pretty good and
have been updated quite a bit although I don't recall which are the
latest and greatest. I know the S3 parts are FAPP not recommended for
new designs (at least by those of us here I expect) and the S3A parts
are pretty old at this point. Anyone, what are the newer S3x parts?

If you want to keep the power supply simple, Lattice has XP and
perhaps XP2 parts that use a single 3.3 volt supply and internally
drop it to the core voltage.


> So if I need power planes for both of these voltages, do they each
> need their own layer or can I arrange it carefully in one layer?

Yes, you can use one layer. I have a very tiny board <1" x 4.5" with
no less than four power planes on one layer, +12, +5, +3.3 and an
audio 3.3. There is another 1.8 volt plane in case I want to use an
FPGA with separate core voltage inputs, but that plane is on a
different layer shared with signal traces. I can't stress enough the
importance of power planes in keeping switching noise down. It is not
just a matter of adding a high frequency capacitor to the power rail,
it acts as a very low impedance transmission line connecting the
capacitors to the power pins of the chip. It is counter intuitive,
but it actually is not so important to keep the caps so close to the
chip if you are using good power planes. BTW, to maximize the
effectiveness of the power planes (read that as minimum impedance) you
want to have the power and ground plane as close together as
possible. 5 mils spacing should be practical and will go a long way
to doing a good job.

I found doing layout to be fun, but very intense! Most design
requires you to go back and forth between specs and data sheets and
the schematic capture package. Layout has some up front work getting
all the inputs and making the footprints, but then it just becomes a
really complex rubics cube with many possible solutions. Your job is
to find one that is pretty good without spending tons of time on it.

When I did my first layout, I contacted a couple of colleges and asked
them to do a design review with me. I was willing to pay them
consulting rates, but I was turned down. It turned out ok in the end,
but there were a couple of things that likely would have been caught
in a review. I am not very busy right now. If you would like and
when you are ready, I'd be willing to go through a design review with
you without charge. I'm pretty bored and would enjoy it.

Rick