>
> Are there any examples out there of how to route memory chips on a
> bus? I'm kind of new to routing and don't really know what the
> strategy is for this kind of thing. I was thinking about this when
> designing a board to interface to expansion headers on a dev board for
> a first prototype, but I couldn't think of a way to do it with just
> two layers, so I gave each chip its own lines in that case since I had
> plenty of I/O.


Now that I think of it, I suppose I could make the bus connection job
a little simpler if I take advantage of the fact that RAM is "random
access," so the address/data line numbers from chip to chip don't
necessarily have to match up. Then the address/data lines could be
connected in whatever order is easiest and cleanest, since on the FPGA
side the data would go in and come out in the desired order either
way.
Would this for any reason be a bad design practice?

Steve