Awesome, thanks for the good information!

John,
I don't think I can get away with only the outer two rows of balls,
I'll probably need the two inside of that as well-- I was thinking of
breaking out the outer two on one signal layer and the inner two in
another, as suggested in the Xilinx app note I saw. It was a tight
squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
is the standard offering of the board house we're using.. it's
possible to ask for smaller, for an extra chunk of change.

Are there any examples out there of how to route memory chips on a
bus? I'm kind of new to routing and don't really know what the
strategy is for this kind of thing. I was thinking about this when
designing a board to interface to expansion headers on a dev board for
a first prototype, but I couldn't think of a way to do it with just
two layers, so I gave each chip its own lines in that case since I had
plenty of I/O.
I can imagine a scheme in which there are vias on each line going into
the first chip, connecting to wires on another layer to carry the
lines to the other chip where they are brought back to the component
side with more vias, but that's all I can come up with off the top of
my head

RCIngham, thanks for the heads-up on the EEPROM. I guess that the idea
is to have non-volatile data in it, and copy it to a section of SRAM
on power-up and then just read from SRAM during normal operation, but
I will still probably have to think about the time to 'Z' when
designing that data transfer part of the software.

cheers,

Steve