>Thanks for the input so far, guys!
>
>I will have two SRAM chips and one parallel EEPROM in one memory
>space, and one additional RAM chip in a separate memory space so I
>know for sure that that one gets its own dedicated address/control/
>data lines.
>I was just wondering if the signal integrity would be hurt by extra
>loading in chaining up the ones that are on the same bus, but I had a
>hunch that at these speeds it wouldn't be such a big problem.
>

I suggest checking the data bus turn-off (->Z) time of the EEPROM. It migh
be rather long, meaning that an EEPROM read followed by an SRAM acces
causes data corruption.

If it is too long, either put an extra buffer with fast turn-off on th
board, or else use dedicated data signals and mux it in the FPGA.


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