Hi guys.. I'm getting ready to start working on my first board layout
with a BGA package (FG456). First will be a prototype for sure.
I was just wondering a few things...

Probably the critical part of my design will be interface to a few
asynchronous SRAMs.

In a relatively low speed design (buses at 10-25MHz) do I need to
worry about things like termination and trace length on the RAM buses?
Should I dedicate address/data pins to each chip in a shared memory
space, or is it better to daisy chain them on a bus? (It seems to me
that routing will be a little easier if each chip gets its own
lines..)

If I won't be using the innermost IO pins, can I get away with a 4-
layer design, two signal layers and power/ground?

Looking at a Xilinx app note with a suggested escape route for this
package, they have three signal layers with 5 mil width traces, the
third of which I believe I can do without...
And lastly, I guess that I will be needing 1.8 and 2.5V supplies, as
well as 3.3V for all of my I/O supplies.. should these all be routed
in the dedicated power layer? If the layer is mostly covered a plane,
which voltage is supposed to be the plane? 3.3V?

And lastly, when connecting I/Os, is there any sensible approach? My
tendency is to want to choose the I/Os so that everything lines up
nicely, but I find it to be a hassle in this case, that in Eagle we
have to connect nets in the schematic first and can't back-annotate
from the board.

Anything else I should be worrying about?

Cheers,

Steve