On Wed, 03 Feb 2010 07:21:13 -0600, dlopez wrote:

> Hi,
> I need to implement CRC detection in a Spartan3 Xilinx FPGA. My data
> stream is coming in one byte at a time, but I do have about 8-10 clock
> cycles between each byte (still tbd!).
>
> If I want to save area, is it better to use a CRC that works byte per
> byte or bit per bit?
>
> Also, any idea where I could find code for the standard polynomials?
>
> Thanks!
> Diego
>
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There is a great polynomial generator on the web,

http://www.easics.com/webtools/crctool