Hi,
I need to implement CRC detection in a Spartan3 Xilinx
FPGA. My data strea
is coming in one byte at a time, but I do have about 8-10 clock cycle
between each byte (still tbd!).
If I want to save area, is it better to use a CRC that works byte per byt
or bit per bit?
Also, any idea where I could find code for the standard polynomials?
Thanks!
Diego
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