On Tue, 2 Feb 2010 18:12:59 -0800 (PST), fpgaasicdesigner wrote:

>and I didn't used an array structure cause it goes to an output I/O of
>a module. That cannot be done in Verilog, that's annoying sometimes
>and there's no difference in the synthesized result for an array or a
>vector, cause an vector is a just a one dimension array... I was able
>to do it in VHDL.

Yes, VHDL has always been a much more expressive language
for synthesisable designs. Only now is SystemVerilog
beginning to catch up.

> Perhaps System Verilog is able to do that ?

Yes, it is. Ports can be of any array type, and all the
new user-definable data types (struct, union, enum) can
also go on ports. At last!

And the great majority of mainstream tools now fully
support that part of SystemVerilog for both simulation
and synthesis.
--
Jonathan Bromley