On Feb 2, 5:15*pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Feb 2, 4:15*pm, fpgaasicdesigner <fpgaasicdesig...@gmail.com>
> wrote:
>
> > Hi all,
>
> > How can I write more with more elegance this:
>
> > *header={register[0],register[1],register[2]}.
>
> > Meaning having a for loop to concatenate these bus ?
>
> > Thanks
>
> A generate statement is the way to go for a wide bus. *There really is
> no clean way to reverse the order of a bus so the "generate for" will
> take care of it in a somewhat better fashion. *But if you have few
> elements, just write it out. *Even 16 elements can come out clean with
> 4 rows of 4 elements each all lined up under each other in a visible
> grid.
>
> * header <= { register[ 0], register[ 1], register[ 2], register[ 3]
> * * * * * * , register[ 4], register[ 5], register[ 6], register[ 7]
> * * * * * * , register[ 8], register[ 9], register[10], register[11]
> * * * * * * , register[12], register[13], register[14], register
> [15] };
>
> It's possible to use bit manipulation or perhaps the width syntax
>
> * header[n] <= register[ n-1 :+ 1 ];
>
> to use a normal for loop but things really start to look unclear to
> the reader.

and I didn't used an array structure cause it goes to an output I/O of
a module. That cannot be done in Verilog, that's annoying sometimes
and there's no difference in the synthesized result for an array or a
vector, cause an vector is a just a one dimension array... I was able
to do it in VHDL. Perhaps System Verilog is able to do that ?